The new 20.1 version of AOC is now the default one in Devcloud. Although it works like a charm I still need to use the old version (19.3) of the compiler because my solution was designed around it. I thought it would be as simple as using the aoc binary located at /glob/development-tools/versions/intelFPGA_pro/19.3/hld/bin/, but, although the compilation completes successfully I get the error CL_INVALID_BINARY (-42) in OpenCL. Can you help me with that?
I am using a script that modifies the PATH variable in the compute node to add AOC v19.3, like this:
The script calls aoc to compile the kernel after that. I want to outline that the compilation ends successfully and aocl env confirms the kernel was compiled with AOC v19.3. The problem comes when I use it a OpenCL program. The 20.1 compiler works like a charm, as I said (I simply have to comment out the line that edits the path to compile with it) and I am able to execute the OpenCL program normally.
If you follow https://github.com/intel/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#devcloud-access..., in the tools_setup, it should have an option for u to select different AOC compiler. But seems like it is not the case. I will get back to you on this.
BSPs for two different versions of the compiler are not compatible with each other. The FPGAs on Devcloud are very likely already configured with a bitstream compatible with the v20.1 compiler and BSP and run-time partial reconfiguration will only work if your bitstream is compiled with the same version of the compiler and against the same BSP.
That makes sense. I guess in that case the solution would be as simple as indicating AOC where the 19.3 version of the Arria 10 BSP is located, right? (which I don't know at the moment, by the way)
I am afraid not; if you want to use a bitstream compiled with a different BSP, then the FPGA must be configured with a bitstream compiled with that BSP through JTAG and the machine has to be rebooted. The static region of different BSPs are not compatible and you cannot partially reconfigure the FPGA with a bistream compiled with a BSP different from the one it is already configured with. Essentially, the only way to use v19.3 on the Devcloud right now is likely asking its admins to downgrade the FPGA firmware to v19.3, which would then mean people will not be able to use the system with v20.1 out of the box and I highly doubt they would want to do that. It is possible to use a newer version of the compiler with an older BSP through backward compatibility, but I am afraid it is not possible to use and older version of the compiler with a new BSP, which means you cannot use the v20.1 BSP with the v19.3 compiler to get around this problem, either. Your only choice is probably to get your design to work with v20.1.
There are two versions of Acceleration Stack 1.2 that uses Quartus version 17.1.1 and Acceleration Stack 1.2.1 that uses Quartus version 19.2.0 . Other versions are not supported and as mentioned the board needs to be flashed with the appropriate board support package (BSP). Hope you can find a workable solution with that in mind.