Using PLLs and FIFOs with AFU for Arria 10 PAC

[DMAHM1]

Hello,

I had a design that I was running on an FPGA (Cyclone V), which included a PLL and several FIFOs.

I am trying to move the design to Arria 10 PAC. However, I don't know how to instantiate PLLs and FIFOs for use with the Accelerator Functional Unit.

I need the PLL to generate a phase-shifted clock and the FIFOs to store some data for processing.

My questions are:

1) The only thing I found for the setting the clocks of the AFU were the key:value pairs "clock-frequency-high" and "clock-frequency-low", which only set the frequency. How can I generate a clock with a specific frequency and phase shift to use with the AFU? This is particularly confusing since PLLs cannot be instantiated in the PR region where the AFU is.

2) As for the FIFOs, would the correct procedure to follow be to create the IP in a regular Quartus project, and then to include it in the files to be used with the afu_synth_setup?

Thank you.

[EricMunYew_C_Intel]

Hi, Dina

Are you referring to a document for AFU for adding PLL and FIFO ? can point me to it ?

Eric

[DMAHM1]

For the question about adding FIFOs, I figured this out. For the PLL, this is the document I am referring to: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-afu-dev.pdf
It only explains how to get two different clock frequencies for the AFU. I guess I wanted to know if it was possible to have a shifted clock, too or not? I tried instantiating a PLL but it didn't work.

[EricMunYew_C_Intel]

Hi, Dina

you can put all your source files in hw/rtl/filelist.txt where you can find it in your AFU directory.