Hi, i am working on a DSO with the ADC (ADS4225) Dual channel 12bit @ 125MS/s each. I want to accomplish saving both those two 12bit channels with a FPGA into a memory chip. I have not devoted too much time on interfacing FPGAs with memory chips but i have been experimenting with a DE0-nano with a FPGA EP4CE22F17C6N on board and a SDRAM.
The ADC data (both channels) will be sent to the FPGA via 6-LVDS channels at 500MS/s when both channels are clocked at 125MHz.
Can this FPGA save the data i want as fast as it is required to a DDR or DDR2 (faster than SDRAM) so that both channels can be filled with data until the memory gets full?
Do i need to consider another FPGA?
Would you be kind to suggest a memory type or even a specific chip?
Are the ALTMEMPHY megafunction controllers suitable for what i need?
I am sorry but your answer is really general. I was hoping for another more detailed suggestion. Thanks though!
Can anybody else be a little bit more descriptive?
You have lots of questions, answers to your questions are very time consuming.
I suppose that if people who are trying to answer questions on that forum will asnwer lots of such question in detail,
they will not manage their work and they will need to ask for a money reward)
So in your case you ask for somebody to do your job, and it is a task that deserves to be paid in my opinion.
Please try to start with somewhat less global.