Why does my cyclone V GX pcie fail to establish communication when the temperature is low?

[DAVID455912142]

We are establishing connections and communication between the PCIe IP core of CYCLONE V GX FPGA and the CPU daughter card. The chip model is 5CGXF7C6F23I.

We conducted experiments by heating the FPGA separately and found that most chips cannot establish a connection with the CPU at a low temperature of -40 degrees Celsius, while they can establish a connection normally at 20 degrees Celsius. Some chips even need to be heated to 40 degrees Celsius to establish a connection, while some chips can also establish a connection at -40 degrees Celsius.

We have also made some attempts to address the issue of abnormal connections in the chips, such as modifying XCVR-RX_SD_THREHOLD and XCVR-RX_COMMON-MODE_VOLTAGE VOLT, but it seems to have been unsuccessful. For example, XCVR-RX_COMMON-MODE_VOLTAGE VOLT can only be set to 0P65V, and modifying XCVR-RX_SD_THREHOLD 3 resulted in an error message: Assignment XCVR-RX_SD_THREHOLD of Calue "3" merges with the valid values of parameters "pm_rx_sd_threshold"

[ventt]

Hi DAVID455912142,

Thanks for reaching out.

Please address the following questions:

1. Are you using PCIe design from our FPGA Design Store? If yes, what is the design example?

2. Besides, does the PCIe link-up succeed only at room temperature?

3. What version of Quartus are you using?

4. Full device OPN of the FPGA

Could you please try the workaround in the below KDB? Note that the devices affected by this issue are Cyclone V GT and ST devices.

https://www.intel.com/content/www/us/en/support/programmable/articles/000077431.html

Thanks.

Best Regards,

Ven

[DAVID455912142]

Hi ven

1. We did not directly use examples from the FPGA store.We used the NIOS II to access the PCIe IP hard core and communicate with the CPU card.

See the attachment for the environment。

2.This time,out of 50 pieces,43 pieces can establish communication at room temperature,while 7 pieces cannot communicate normally at room temperature.These 7 pieces require the FPGA chips to be powered on and work for 3-4 minutes to heat up,after which a restart can establish communication."

3.Quartus14.1!

4.We are currently communicating with our distributor regarding the order number

Thanks.

Best Regards,

david

 

[ventt]

Hi DAVID455912142,

Regarding the 7 pieces that needed to be powered on and work for 3-4 minutes to heat up, were they originally placed at room temperature?

Could you please check the following items?

1. Can the FPGA be configured using JTAG?

2. Can the flash be programmed using JTAG?

3. Can FPGA be loaded from flash using AS configuration - regardless of the temperature condition. Hot/Cold/Room

4. Can you see the CONF_DONE signal turned HIGH after the AS configuration? (flash uploaded its contents into FPGA).

5. Can you share whether the timing closure of the project has violation or not?

Thanks.

Best Regards,

Ven

[DAVID455912142]

Hi ven

1. YES,I Can the FPGA be configured using JTAG!

2. YES,Can the flash be programmed using JTAG!

3.YES, FPGA be loaded from flash using AS configuration - regardless of the temperature condition!

4.I can see the CONF_DONE signal turned HIGH after the AS configuration.

5.Please refer to the attachment for compilation information.

6.Test record are some test records of hardware.

Thanks.

Best Regards,

david

[ventt]

Hi DAVID455912142,

Could you please address the questions in the previous reply?

Thanks.

Best Regards,

Ven

[ventt]

Hi DAVID455912142,

We have not received any response from you on the reply. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

Ven