change the frequency(uClk_usr uClk_usrDiv2)

[HYl]

I am working with Acceleration Stack Version 1.1 . How to change the frequency(uClk_usr uClk_usrDiv2) on the board? Does the uClk_userDiv2 have to be at half of uClk_user? I want uClk_usr to be 300M,and uClk_usrDiv2 to be 150M. what can i do ?

[JohnT_Intel]

Hi,

In order the changes, you will need to make changes on your design .json file. Please refer to https://www.intel.com/content/www/us/en/programmable/documentation/bfr1522087299048.html Chapter 5.3.2.1.7. Specify AFU User Clock Timing

[HYl]

Hi JohnT_Intel: I am working with DCP1.1 , not DCP1.2.

[JohnT_Intel]

Hi,

You may get the older version of document from https://www.intel.com/content/dam/altera-www/global/en_US/others/solutions/acceleration-hub/ias-v1-1-pv.zip. Then please open ug-afu-dev-v1-1.pdf chapter 4.3.2.1.7 Specify User Clock Timing. The method to make the changes is almost the same with the version 1.2 has more improvement.

[HYl]

Hi, I already have done the necessary work according to ug-afu-dev-v1-1. I finally get .gbs，but i find the real uClk_usrDiv2 period is not correct.I find uClk_usr is 300MHz,while uClk_usrDiv2 is 150M ,not 100MHz.

[JohnT_Intel]

Hi,

For version 1.1, the uClk_usrDiv2 will always be half of uClk_usr frequency which is why you are observing 300Mhz and 150Mhz respectively. If you would like to set uClk_usrDiv2 to 100Mhz then I would recommend you to update your DCP version to 1.2.

[HYl]

I am wondering why there is a frequency relationship limitation between uClk_usr and uClk_usrDiv2.Can i remove the limitation? Is there someting special?

[JohnT_Intel]

Hi,

If you look at the document for v1.1, it is stated that "uClk_usrDiv2 (fixed at half frequency of uClk_usr)". So there is no way for you to changed it as it has been fixed on the design. So if you move to v1.2, you will have the flexibility as the feature as been enabled.