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create_generate_clock

fxu001
Novice
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If my source clock pass two PLL and new clock divided 3 to create new clock, how do I use create_generate_clock?

Since Altera used derive_pll_clocks, it little bit confuse me now. I think It should do in the last stage to use create_generate_clocks because Altera has variable erive_pll_clocks, so the -source [clock_pin] should be the first drive pll pin, am I correct?

 

Thanks,

 

-Fred

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Rahul_S_Intel1
Employee
362 Views

Hi ,

Kindly fine the places where

 

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fxu001
Novice
362 Views
Hi RSree Which value should I set for the JESD204B input and output ports as following Snipping . Please give ASAP [cid:e99ad932-779a-4345-bcae-8419d3353521] [cid:7a289d19-bc51-483b-a1ef-410d353a6a2a] Thanks, -Fred
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