In my openCL kernel , part of the function i want to wirte by RTL code. and now the RTL is function simulation correctly . i have read the "Intel® FPGA SDK for OpenCL™ ProEdition Best Practices Guide" for many times! Still some part not well understand::
- my RLT output is parallel output 128bit data(here i want it parallel output), named reg [127:0] dataout in rtl. that is 4 32 bit int data for kernel, how opencl kernel code received the 128bit data(4 int ), like this:
for(int i = 0; i <4;i++)
how to do here???
2 if the RTL part has two output data return to the opencl kernel , dataout1[127:0]( that is 4 32bit int data for kernel ), data_out2[127:0] (16 8bit char for kernel). how to do ???
Thanks for your help!!!
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_programming_guide.pdf in Chapter 5.6 have the example of implementing arbitary precision integer which is suitable to your situation.
For the information and function of "intn" can be found in Chapter 4.4 as link below:
Thanks for your help!
Again , the 128bit RTL data is 4 int data, for example ,
(in RTL)dataout[31:0] is my data1( int for kernel),
(in RTL)dataout[63:32] is my data2( int for kernel),
(in RTL)dataout[95:64] is my data3( int for kernel),
(in RTL)dataout[127:96] is my data4( int for kernel),
can i define a 128 bit data "mydata " in kernel , to received the RTL 128bit dataout, and then split the kernel 128bit "mydata" into 4 32bit without any side-effect????
I haven't do this before, I would like to know why you want to split the data?
The question ask is due to I would like to know the data separate I in host application level or kernel level.