receive higig2 Ethernet packet

Application Acceleration With FPGAs

Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs

receive higig2 Ethernet packet

592 Views

Device:10AX115S3F45E2SGE3 quartus16.0

When i use ipcore"Low Latency 40G/100G Ethernet" receive higig2 Ethernet packet.Some times ,the ipcore output startofpacket data "fb 00 00 00 00 ...",the "00 00 00 00" is not right data.And the FCS bytes of endofpacket is wrong when calculate including "00 00 00 00" .When the "00 00 00 00" calculation is not included, fcs is correct .And the receive package number is less than send.How to deal with it ？Thanks.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.