By Mark Gardner, Vice President and General Manager of the Packaging and Test Business Group, Intel Foundry
Rapid growth in compute requirements for system on chips (SoCs), artificial intelligence (AI) accelerators, and networking devices is pushing traditional semiconductor packaging to its limits. To move beyond the restrictions of single-reticle die sizes, the industry has adopted package architectures that enable combining multi-reticle die complex sizes, including high-bandwidth memory (HBM), in a single package. These multiple reticle systems allow for greater compute density and more complex integration than monolithic chips can provide. This evolution requires innovative packaging architectures to support expanded area, higher interconnect density, and enhanced power and thermal management to meet the needs of next-generation devices.
One method for creating die complexes larger than one reticle is to attach smaller die to an interposer. Manufacturing this type of interposer requires reticle stitching, which is complex and expensive. A more cost-effective alternative involves embedding silicon bridges within the substrate. By interconnecting smaller, high yield chiplets only where needed, bridges allow manufacturers to overcome reticle limitations without the high cost of a full-scale stitched interposer.
For ultra-large form factor devices, Intel Foundry offers Embedded Multi-die Interconnect Bridge-T (EMIB-T), an advanced packaging technology that combines the high bandwidth interconnect benefits of EMIB 2.5D and adds through-silicon vias (TSVs) for improved power delivery. EMIB-T enables systems with a total area exceeding 6x the reticle size today, scaling greater than 8x the reticle size this year and more than 12x by 2028. For foundry customers, these advanced large-body packages are now essential enablers, allowing them to scale beyond reticle constraints and integrate more functionality on-package. This, in turn, optimizes performance, cycle time, yield, and cost in AI, high-performance computing (HPC), and other demanding workloads.
How Reticle Limits Drive the Need for Advanced Packaging
By utilizing advanced reticle technology, customers benefit from precise patterning that ensures high-quality, distortion-free chip features, even as designs grow more complex. The reticle defines and transfers intricate circuit patterns on to the wafer with exceptional accuracy, enabling higher yields and consistent device performance. This capability supports the reliable manufacturing of sophisticated chips and accelerates your path to market with innovative semiconductors.
However, reticle exposure fields are inherently size-limited, restricting the maximum area of a single monolithic die. As compute demands push beyond this boundary — particularly in AI accelerators and HBM-integrated systems — advanced packaging enables integration at scales larger than a single reticle field. Interposers are one of the solutions for connecting multiple die with ultra-high-density interconnects. When an interposer must exceed the 1x reticle size, it is fabricated using reticle stitching, where adjacent exposure fields are precisely aligned and joined to form a continuous substrate. This approach enables silicon footprints that scale beyond conventional lithographic limits while preserving fine-pitch interconnect performance.
By overcoming reticle field constraints, advanced packaging enables larger die complexes and expanded package form factors. This allows customers to combine diverse components such as central processing units (CPUs), graphics processing units (GPUs), and HBM into a single tightly integrated environment. The result is reduced latency and massive bandwidth through ultra-high-density interconnects. These large silicon platforms power AI and data centers, high-end 5G and 6G networking devices that require massive input/output (I/O) counts, and advanced driver-assist systems (ADAS) that consolidate multiple computing functions into a single robust package.
EMIB-T: The Cost-Effective Solution for Expanding Reticle Limits
Intel Foundry takes a differentiated approach to expanding compute beyond reticle limits through EMIB-T technology. Rather than relying on large, costly-to-manufacture interposers, EMIB-T integrates multiple silicon die — including compute, HBM memory, and I/O — within a single package using high-density silicon bridges embedded in an organic substrate. This approach enables ultra-high-bandwidth die-to-die connectivity while maintaining design flexibility across heterogeneous process technologies. By allowing diverse chiplets to be combined efficiently and cost-effectively, EMIB-T delivers scalable system performance without the complexity and manufacturing overhead of full-size interposers.
By combining EMIB-T with Foveros 2.5D or Foveros Direct 3D packaging to make EMIB 3.5D, customers can integrate different types of dies using various process nodes into a single, three-dimensional interconnect system. The hybrid architecture uses the vertically stacked chiplets of Foveros with the silicon-embedded bridge of EMIB-T to deliver an optimized balance of package size, compute performance, power usage, and cost savings. EMIB 3.5D addresses the downsides of reticle size limits and interconnect constraints, enabling a significantly expanded area of silicon for building complex ultra-large systems.
Comparing EMIB-T to Other 2.5D Packaging
Other foundries offer 2.5D packaging with an interposer beneath all the chips. However, these interposers are expensive and difficult to manufacture once they exceed a certain size. As another option, other foundries may offer bridge-based packaging by placing local silicon interconnect (LSI) bridges in the interposer, which requires more assembly steps than traditional interposer designs.
Figure 1. EMIB-T can provide cost advantages by using less silicon and offering higher wafer utilization and yield compared to other silicon or redistribution layer (RDL) interposer architectures.
From a manufacturing standpoint, EMIB-T and full interposer solutions follow fundamentally different process flows. In an EMIB-T design, small silicon bridges are fabricated on a wafer at very high density, enabling approximately 90% wafer utilization (see Figure 1). These bridges are then embedded into large-format organic rectangular panels, which are singulated into individual rectangular substrates, leading to overall high material utilization. Compute die, HBM stacks, and I/O components are subsequently attached to these substrates, with the silicon bridges providing localized, high-density interconnect only where required.
By contrast, large interposer-based approaches require fabrication of an entire interposer on a wafer before assembly. While local silicon interconnect chiplets for RDL-based interposers can be manufactured efficiently, the full-size interposer must match the total package footprint for both interposer types. For large form factor devices greater than 8x reticle complexes, this can reduce wafer utilization to as low as 60%. The interposer must then be attached to a substrate, requiring significant wafer capacity and introducing additional process complexity.
As a result, EMIB-T delivers not only superior silicon efficiency but also a packaging flow inherently aligned with panel-based manufacturing. By localizing high-density interconnect only where it is needed and leveraging large-format substrate panels, EMIB-T maximizes utilization across both silicon and substrate processes. This structural advantage reduces cost today and positions EMIB-T architectures for scalable, panel-driven manufacturing as package sizes continue to grow — particularly in advanced multi-HBM configurations.
Figure 2. The EMIB technology family delivers scalability now and into the future to support demanding applications.
Intel Foundry’s approach allows for ultra-large die complex sizes and corresponding package form factors that are impossible with standard interposers. Expanding from our current capability of approximately 6x the reticle size for a die complex, Intel Foundry is enabling complexes greater than 8x the reticle size (roughly 6,800 mm²) in 2026, scaling to greater than 12x the reticle size (around 10,000 mm²) accommodating equal to or greater than 16 HBM4/HBM5 stacks using 30 or more EMIB-T bridges by 2028 (see Figure 2).
How Intel Foundry’s Approach Differs from the Industry
While Intel Foundry and other foundries use advanced multi-die packaging technologies to create chips that exceed the reticle limit, our approach differs in implementation and ecosystem strategy — we’re a full stack co-optimized systems foundry. We offer an open, standardized ecosystem and a modular approach using our proprietary packaging technologies to mix and match dies from various foundries, making it easier for customers to port designs without major modifications, which in turn reduces redesign cycles.
To achieve this open approach, we champion standards such as the Universal Chiplet Interconnect Express (UCIe), which allows chiplets from different vendors and process nodes to communicate. Alongside UCIe, Intel Foundry supports open die-to-die interconnect standards to enable modular architectures through the Open Compute Project’s (OCP) Bunch of Wires (BoW) specification. We also partner with major electronic design automation (EDA) companies to ensure tools and design kits (PDKs) are validated for Intel Foundry's process technologies.
The Future is Open
The future of advanced packaging is open at Intel Foundry. We’re fostering a modular, chiplet-based world where customers can access our broader technology stack without immediate foundry lock-in. We can help simplify the supply chain by offering a more streamlined assembly process compared to traditional methods, making complex chiplet designs more accessible and faster to market.
We overcome reticle limits by providing a powerful, cost-effective, and flexible platform that can handle massive chiplet integration, setting a new benchmark for performance and scale in advanced packaging.
How can we help you build your ultra-large packaging designs? Visit intel.com/foundry or reach out to us at foundry.contact@intel.com.
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