Systems of Chips: Exploring the Evolving Future of Chiplet Design Capabilities

By Salem Abdennadher, Principal Engineer, Intel Foundry

Foundries worldwide will play a pivotal role in making multi-vendor “plug-and-play” chiplet designs a reality. This key point emerged last week at Chiplet Summit 2026, an annual conference highlighting the trends and challenges of open chiplet ecosystems. In this chiplet era, leading foundries are expanding beyond pure wafer fabrication to support advanced packaging and heterogeneous integration, enabling high-performance systems of chips that combine components from multiple process nodes. This shift is driven by the need for performance, cost efficiency, and flexibility in an industry now dominated by artificial intelligence (AI) and high-performance computing (HPC). Chiplets are increasingly becoming a key vector to deliver Moore’s Law integration benefits to create smaller, faster, and more affordable electronic systems.

Adopting a Multi-Vendor Chiplet Ecosystem

Chiplets can enable faster time to market in two ways: first, specialized small dies can be used in multiple product designs, and second, through the reuse of existing chiplets from previous generations. Since chiplets are a high work product asset, die-related reuse can act as a strong leverage vehicle to improve cost, schedule, and quality. For the chiplet approach to become mainstream, it must enable seamless interoperability among components from multiple vendors, work across both fabless companies and integrated device manufacturers (IDMs), and be supported by foundries capable of reliably producing these designs at high volume. While various companies have already brought products to market based on this design approach, the ultimate goal is for the industry to adopt a multi-vendor chiplet marketplace ecosystem, where system designers can pick and choose their preferred chiplets from multiple vendors.

Building an open chiplet economy and marketplace, complete with composable and reusable solutions, is a multi-year journey with significant technical barriers due to divergent standards, lack of compatibility, bottlenecks in testing and validation, and issues with scalability and future-proofing. To move the process forward, Intel Foundry created the Intel Foundry Accelerator - Chiplet Alliance to help customers access a comprehensive portfolio of validated tools, intellectual property (IP), and design services from trusted ecosystem partners.

Collaborating on Standards for Interchangeable Chiplets

To allow industry-scale reuse, foundries are crucial enablers of the transition from monolithic design to a modular approach. With costs increasing for advanced nodes, advanced packaging is the key to this vision. The next dimension in technology scaling is 2.5D and 3D heterogeneous integration. Intel Foundry and others in the industry have been actively collaborating to support this trend with standards to support a thriving chiplet ecosystem.

Among the innovative standards that have paved the way for multi-die systems, the Universal Chiplet Interconnect Express (UCIe) focuses on allowing an open, broadly interoperable and conformance testable chiplet ecosystem with ubiquitous in-package chiplet interconnect. Multiple other open standard initiatives also help to enable an open chiplet economy, including the UCIe Interop and Compliance, Advanced Microcontroller Bus Architecture (AMBA) Chip-to-Chip (C2C), JEP30 extension, and Open Compute Project (OCP) 3DIC Design Kit (3DK).

Using Cross-Foundry Validation for an Open Chiplet Economy

To help enable an open chiplet economy, foundries worldwide have been developing and offering sophisticated 2.5D and 3D stacking packaging flows, which are essential for connecting multiple chiplets in compact, high-performance systems. Chiplets also allow designers to use different process nodes from various foundries for different functions, such as a leading-edge node for compute and a mature, cost-effective node for input/output (I/O) functions.

When foundries enable this level of heterogeneous integration, they contribute to a more resilient supply chain by enabling cross-foundry integration, reducing the risk associated with relying on a single manufacturing source. Collaboration and validation remain key pillars in the future of chiplet design. Foundries have been working closely with electronic design automation (EDA) providers, IP vendors, and packaging partners to ensure validated design flows and robust manufacturing processes for multi-die systems.

The Intel Foundry Advanced Packaging Advantage

At Chiplet Summit, I shared how Intel Foundry has been driving multi-die design innovation forward. Recently, Intel Foundry and IP ecosystem partners have extended their collaboration to the Embedded Multi-die Interconnect Bridge-T (EMIB-T) advanced packaging solution. EMIB-T combines the high bandwidth interconnect benefits of EMIB 2.5D and adds through-silicon vias (TSVs) for improved power routing. Foveros Direct 3D supports die-to-die (D2D) high density interfaces using Intel 18A and Intel 14A with an active base die. The combination of EMIB-T 2.5D and Foveros Direct 3D, known as EMIB 3.5D, supports package size scaling. This enables multi-chip, multi-node architectures to more intelligently allocate workloads across both proprietary and ecosystem IP, delivering a more optimized balance of cost and performance.

Chiplet Design: Looking Ahead to 2030

As foundries evolve into advanced packaging providers, they enable heterogenous integration by working with EDA vendors to drive standardization. Foundries are shifting from solely manufacturing monolithic dies to assembling components from different nodes, such as AI and I/O, into high-performance systems with R&D investments in 2.5D and 3D packaging, and hybrid bonding. This pivot is expected to dominate chip design by 2030.

Learn more about how Intel Foundry’s systems foundry approach can help make your chip designs a reality. Reach out to us at intel.com/foundry and foundry.contact@intel.com.