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Intel Agilex® 7 FPGAs with R-Tile Deliver Industry-Leading Bandwidth for CPUs – Now in Production

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 As innovations drive new connectivity and processing models from the edge to the cloud, there is a growing need for flexible hardware solutions. With the ever-increasing bandwidth requirements across markets, the need for faster and more flexible devices has never been greater. Intel Agilex® 7 FPGAs with R-Tile have the high bandwidth interfaces and flexible programmable logic needed to address these requirements. R-Tile-based Intel Agilex 7 FPGAs are now in production. 

Market adoption of FPGA accelerators has steadily increased in recent years and with the rollout of R-Tile-equipped FPGAs, newer high-performance accelerators are now possible. FPGA accelerators can offload tasks from the host CPU, freeing up CPU cores and reducing the total power consumed, enabling total cost of ownership (TCO) savings.  If you are an end user, an IT professional, or a cloud service provider and haven’t yet explored using FPGA accelerators, now is a good time to start.

  • Cloud providers using FPGA accelerators can support more users and generate more licensing dollars from the newly available CPU cores
  • OEMs leveraging FPGA accelerators can save money and use less power

The Intel Agilex® 7 FPGA product family has been designed to address these needs and R-Tile-based devices are now in production.

Intel Agilex® 7 FPGAs are built with a heterogeneous multi-die architecture, with an FPGA fabric chiplet in the center connected to transceiver chiplets via Intel’s embedded multi-die interconnect bridge (EMIB) technology. Each chiplet, or tile, is a small integrated circuit die containing a well-defined subset of hardened functionality. These chiplets enable a cost-effective approach to the in-package high-density interconnect of heterogeneous chips. This approach allows Intel to address a broad array of applications with tailored, flexible solutions. Thus, enabling customers to realize connectivity topologies within a single device that previously would have required multiple devices.

Many of the Intel Agilex® 7 FPGA package combinations include the R-Tile chiplet, designed to support industry-leading bandwidth when connecting to high-performance CPUs either via PCI Express or Compute Express Link (CXL) protocols. The R-Tile chiplet combines hard intellectual property (IP) blocks and soft IP code for PCIe 5.0 x16 and CXL 1.1/2.0, providing a high degree of flexibility across Networking, Cloud, Data Center, High-Performance Computing, and many more markets. 1 lists the key technical features supported by the R-Tile.


Figure 1. Intel Agilex® 7 FPGA with R-Tile Block Diagram

R-tile Feature Table.jpg

Table 1. Intel Agilex® 7 FPGA R-Tile Key Features

The production qualification of R-Tile triggers the production release sequence for seven device densities across four different packages within the Intel Agilex® 7 FPGA I-Series devices enabling customers to leverage Intel Agilex® 7 FPGA fabric performance / per watt leadership on their new designs. Built on the Intel 10 nm process technology, both the Intel Agilex® 7 FPGA programmable logic and R-Tile chiplet leverage Intel’s robust supply chain with advanced manufacturing and test capabilities to deliver production solutions to standard lead times. Additional device density and package options will reach production once the Intel Agilex® 7 FPGAs M-Series with R-Tile transition from sampling to production.

Combining R-Tile capabilities with other Intel Agilex® 7 FPGA chiplets, such as the recent production-released F-Tile, creates a flexible, high-performance FPGA suited for next-generation accelerators such as SmartNICs, IPUs, and computational storage solutions.

To learn more about leveraging R-Tile-based Intel Agilex® 7 FPGAs for next-generation high-performance designs, visit the FPGA Leadership Page.

For more information about the devices and solutions discussed in this blog, contact your Intel salesperson directly.