- Partial reconfiguration and encrypted partial reconfiguration bitstream support Intel Stratix® 10 devices
- Enhanced handling of Intel FPGA designs with large inferred RAM requirements
- Platform Designer enhancements include:
► Added support for system HDL parameters. Now you can pass parameter values from parent systems to subsystems and from system to instantiated IP blocks by adding HDL parameters to systems and assigning values to instance HDL parameters that are exposed.
► Added new interconnect parameter: Enable all pipeline stages.
► Added “Add All Pipelines” and “Remove All Pipelines” buttons to MemoryMapped Interconnect tab.
To go directly to the Intel Quartus Prime Pro Edition download page, click here.
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