TÜV-Certified Dual-Axis Motor Control with Functional Safety on Agilex™ 5 SoC FPGAs

Model-based FPGA design offers functional safety for industrial drives, robotics, and automotive systems 

Raising the Bar for Safety and Performance in Motor Drives

As industrial automation, robotics, and automotive systems grow more sophisticated, the need for certified functional safety alongside real-time control performance is a prerequisite. In a new demonstration, Altera and MathWorks showcase a TÜV-certified Cat. 3 PLd dual-axis motor control system built on Agilex™ 5 SoC FPGAs, combining model-based development with flexible, portable safety architectures. This demo reveals how engineers can achieve both high-performance motor control and functional safety certification quickly, with tools they already know, like MATLAB* and Simulink*.

Watch the full demo on YouTube

Model-Based Design Flow with MATLAB, Simulink, and DSP Builder

At the heart of the development is a model-based design approach:

• Altera’s DSP Builder Advanced Blockset integrates directly with MATLAB and Simulink, allowing control engineers to design, simulate, and optimize algorithms at a system level.
• These algorithms are then automatically compiled into synthesizable RTL for direct implementation in the FPGA fabric, streamlining the flow from model to silicon.
• For this demo, simulated industrial motor models replace physical motors, enabling parameterized testing across different load conditions, drive topologies, and performance goals without re-hardware iteration.

This shortens development cycles and allows rapid design exploration while preserving high fidelity between simulation and deployed hardware.

Dual-Channel Functional Safety Architecture: Diverse and Redundant

Functional safety is achieved through dual, independent speed checkers:

• Checker channel 1 runs entirely in the FPGA fabric.
• Checker channel 2 executes as software on the ARM*-based Hard Processor Subsystem (dual-core Cortex-A55 and dual-core Cortex-A76 processors along with hardened peripherals) embedded within the Agilex 5 SoC FPGA device.

This checker redundancy mitigates both systematic faults (software bugs and toolchain errors) and random hardware faults (e.g., single-event upsets), satisfying the stringent TÜV Rheinland Cat. 3 PL d certification requirements.

By using both hardware and software domains, the system ensures orthogonal safety validation paths, increasing fault tolerance and simplifying safety case documentation for industrial, automotive, and robotics applications.

Portability Across Altera FPGA Families

The demo is designed for portability:

• If an application doesn’t require the sophistication and performance of the integrated Arm processors, the control and safety functions can be ported to Altera’s Nios® V RISC-V-based soft processors.
• Using the Nios V soft processor provides a flexible, lightweight alternative that maintains real-time performance and increases the number of Altera FPGA families to choose from.

This makes the solution adaptable across multiple FPGA families and suitable for a spectrum of industrial products, from low-cost edge motor controllers to complex multi-axis robotic arms, without redesigning core safety logic.

Real-Time Performance and System Responsiveness

Beyond safety, the Agilex™ 5 SoC FPGA architecture enables:

• Low-latency deterministic control using FPGA hardware for critical paths.
• Software programmability on Arm processors or Nios V cores for supervisory functions, diagnostics, and runtime updates allows for system responsiveness for equipment already deployed in the field.
• Fine-grained motor simulation and high-speed, low-jitter signal paths, critical for robotics, servo drives, and autonomous mobility.

With simultaneous deterministic control and flexibility for edge analytics or safety monitoring, the system achieves a nice balance of performance, safety, and adaptability.

Reducing Certification Work Frees Up Time for Innovation

The combined MathWorks and Altera toolchain simplifies:

• Algorithm design and verification via DSP Builder
• Automatic HDL code generation via DSP Builder
• Safety validation with TÜV-reviewed architecture and documentation
• Hardware validation using Altera FPGAs accelerates overall feature development

This integrated flow reduces time-to-certification and development risk, critical factors for engineers to bring safety-critical innovations to market fast.

Accelerate Your Functional Safety Designs

→ Explore the Agilex™ 5 Functional Safety Reference Design

Go to Altera GitHub

→ Learn more about Agilex 5 FPGAs and SoCs:

Go to Altera Agilex 5 product website

→ Learn more about Altera’s DSP Builder Software with links to MathWorks MATLAB* and Simulink*:

Go to Altera DSP Builder software product website

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