Many Intel® FPGAs— including Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10, Stratix® V, Arria® V, and Cyclone® V FPGAs and SoC FPGA— support the JESD204B multi-gigabit serial data link for data converters (analog to digital converters (ADCs) and digital to analog converters (DACs)). In addition, Intel Agilex and Intel Stratix 10 FPGAs and SoC FPGAs support the newer and faster JESD204C interface standard. Intel Agilex FPGAs and SoC FPGAs that incorporate F-tiles support all JESD204C data rates allowed by the standard, up to 32 Gbps/lane.
The JESD204 serial interface standards replace the older parallel data interfaces previously used by slower data converters. These new standards radically increase data rates while they reduce the number of I/O pins needed to connect these converters to other logic devices, including FPGAs. At the same time, employing the JESD204 interface standards cuts the interface power consumption needed to support high-speed transfers between these data converters and the attached digital logic chips. Reducing the number of interconnects simplifies circuit board layout, permits the use of smaller converter IC packages, and shrinks board-level form factors while boosting system performance.
Because of these many system design advantages, the JESD204B and JESD204C specifications have become broadly implemented industry standards. Several high-speed data converters from multiple vendors support these standards and these JESD204-compliant converters are increasingly used for a variety of high-frequency, wireless, and RF applications including wireless infrastructure radios (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA), software-defined radio (SDR), portable instrumentation, medical ultrasound, and military/aerospace applications such as radar and secure communications.
Intel has developed specialized FPGA intellectual property (IP) for the JESD204C interface and has performed many JESD204B and JESD204C interoperability tests between Intel FPGAs and a variety of data converters from Analog Devices (ADI) and Texas Instruments (TI) using this IP. Intel has published application notes and reference designs based on these successful JESD204C interoperability tests and has now produced a 5-minute demo video that demonstrates the performance and capabilities of a JESD204C interface implemented using F-tile high-speed transceivers in an Intel Agilex I-Series FPGA.
The demo shows an Intel Agilex I-Series FPGA with sixteen F-tile general-purpose transceivers, each configured for JESD204C operation, externally looped back through an FMC+ card. Each of the 16 JESD204C lanes in this first portion of the demo operates at 28 Gbps, which is the maximum data rate supported by the FMC+ card. However, the JESD204C specification encompasses data rates to 32 Gbps/lane (the earlier JESD204B specification was limited to 12.5 Gbps/lane). Intel Agilex FPGAs with F-tile transceivers can achieve that faster data rate, and the video demo employs the Intel Agilex transceivers’ internal loopback mechanism to show the Intel Agilex I-Series transceivers working at 32 Gbps while configured for JESD204C operation. In all of the tests in the demo, the JESD204C lanes implemented with the Intel Agilex FPGA operate without error.
If your next project involves high-speed ADCs and DACs and you need JESD204B or JESD204C capabilities to interface with these converters, you should watch the new video demo. Click here.
For more information about the Intel JESD204B and JESD204C IP for Intel FPGAs, including application guidance and design examples, see:
- JESD204C Intel FPGA IP User Guide
- JESD204C Intel Agilex FPGA IP Design Example User Guide
- JESD204C Intel Stratix 10 FPGA IP Design Example User Guide
- JESD204B Intel FPGA IP User Guide
- JESD204B Intel Agilex FPGA IP Design Example User Guide
- F-Tile JESD204C Intel FPGA IP User Guide
- F-Tile JESD204C Intel Agilex IP Design Example User Guide
- F-Tile JESD204B Intel FPGA IP User Guide
- F-Tile JESD204B Intel FPGA IP Design Example User Guide
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