The latest release of the Intel® Quartus® Prime Software v22.2 adds even more intuitive features and improvements that make it easier for you to design with Intel® FPGAs, including the new Intel® Agilex™ FPGAs. These new features and improvements include:
- Improved Quality of Results (QoR) for Intel® Agilex® FPGAs along several critical design dimensions including up to 40% lower power consumption and up to 50% higher Fmax performance compared to Intel® Stratix® 10 FPGAs†.
- Numerous Nios® V soft processor updates including the new Eclipse-based Ashling RiscFree IDE–an integrated software development environment with full source and project creation, editing, build, and debug support–tailored for use with Intel® FPGAs. (The Nios V processor is the newest generation of Nios soft processors for Intel FPGAs and is based on the RISC-V instruction set architecture (ISA). See “Introducing Intel’s Next-Generation of Nios® Soft-Core Processor: Nios® V Processor.”)
- New: Design Netlist Infrastructure (DNI), a unified design database that makes the Intel Quartus Prime Software run faster with an application interface that’s cleanly separated from the database layer, an easy-to-use data model, and a uniform and comprehensive scripting interface
- New: RTL analyzer, a visual netlist analysis tool for viewing and probing your Register Transfer Level (RTL) netlist
- F-Tile support and Tile Interface Planner for Intel Agilex FPGAs including a Tile Assignment Editor and interactive placement of multi-rate intellectual property (IP) and user-defined Dynamic Reconfiguration Groups
- Design Assistant now has new and improved design rules for synthesis, clock domain crossing (CDC), reset domain crossing (RDC), dynamic reconfiguration (DR), memory initialization, and additional linting rules to help avoid RAM corruption
- Several new multi-rate IP blocks including Ethernet, CPRI, and DirectPHY that target Intel Agilex F-Tile devices
- New reports for global routing congestion visualization, unexpected clock crossings, and a support-logic generation report for Intel Agilex FPGAs with F-tiles
- Platform Designer support for the AXI Timeout Bridge
- AXI4-Lite support for the AXI Pipeline Bridge
- RAM inferencing with clock enable usage to reduce memory power consumption
- Advanced Link Analyzer now supports high-speed Ethernet SerDes ports for F- and R-Tiles in Intel Agilex FPGAs with simulation engine enhancements and improved COM/ERL support
- Wind River Linux Long Term Support for Intel Agilex FPGAs and Intel® Stratix® 10 SoC FPGAs, including both source code and binary distributions
- And much more…
The new Intel Quartus Prime development software version 22.2 is available for immediate download. Download now.
† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit our performance index page.
Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details.
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