I'm having problems making write-combining memory coherent to a graphics card. Here's the hardware: Pentium-M processor i875P chipset ATI M9 graphics chip via AGP
I know the i875 is not specifically designed for Pentium-M's but I can't see how that is related to my problem (this is a custom board for a proprietary product).
Problem summary: Software writes graphics commands (DMA lists) to the graphics aperture which is part of system memory and has a write-combining cache policy. When we want the M9 to execute these commands we perform an SFENCE instruction to flush the write-combining buffers and trigger the M9 to consume the data. Sometimes, the M9 sees old data.
I have tried other means to force the write-combining buffers to flush (io port writes, etc) and have also tried the clflush command. The io-port writes seem to make the problem less frequent but it still happens.
I have viewed the AGP transactions on an analyzer and, in the failure case, I see the old data coming across.
Perhaps I don't understand correct operation of the GART? Our GART establishes a one-to-one mapping of the system memory aperture to an area of address space that is beyond physical memory. We give these higher addresses to the M9. This prevents cache snoop cycles on the FSB when the M9 is bus-mastering data from system memory.
When you say "our GART" what do you mean. The GART is controlled by a driver in the OS. What OS are you using? You are correct in what you are saying about how it works though. If you are seeing old data coming across you mean from the graphics driver correct?