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AStoj1
New Contributor I
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Ethernet Compliance Test I210-AT 10Base-T/100Base-TX

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Hi

I want to run Ethernet Compliance Tests 10/100Mbps with I210-AT.

Are there any information available? I can not find anything in the datasheet.

E.g. create 100Mbps MLT-3 Random Test Pattern.

I can only find Test Mode Register Bits (15:13) in 1000Base-T Control Register (Page 0, Register 9) for Gigabit.

What is the purpose of 100 MB test select bits 3:2 of Copper Specific Control Register 3 - Page 0, Register 23 ?

What can I do with the PRBS Control - Page 26, Register 23 ?

Thanks for your help

Andrija

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1 Solution
AStoj1
New Contributor I
1,025 Views

IEEE 10Mbps Tests:

 

• Setup For All patterns – This needs to be done before sending packets with the listed payload below for each test. Ensures the link is forced up so packets will send and that no other 100/1G test modes are running.

 

o Write MDIO Phy Register 0x10, Turn off bit 10

 

o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3

 

o Write MAC Register 0xE14, Turn off bit 5

 

o Write MDIO Phy Register 0x10, Turn on bit 10

 

o Write MDIO Phy Register 0x16, Set value to 0x6

 

o Write MDIO Phy Register 0x10, Set Value to 0x0

 

o Write MDIO Phy Register 0x16, Set Value to 0x0

 

o Write MDIO Phy Register 0x0, Set Value to 0x0

 

14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 5MHz) – Send 1500 Byte Packets containing AA pattern as the packet payload.

 

14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 10MHz) - Send 1500 Byte Packets containing FF pattern as the packet payload.

 

14.3.1.2.1 - Harmonic Content, All Ones Signal - Send 1500 Byte Packets containing FF pattern as the packet payload.

 

14.3.1.2.1 - Differential Output Voltage Template - Send 1500 Byte Packets containing Random data as the packet payload.

 

14.3.1.2.1 - TP_IDL Waveform Output – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0.

 

14.2.1.4 - RD Circuit Differential Input Impedance (Rx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0.

 

14.3.1.2.2 - TD Circuit differential Output Impedance (Tx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0.

 

14.3.1.2.5 - TD Circuit Common-Mode Output Voltage - Send 512 Byte Packets containing Random data as the packet payload.

 

14.3.1.2.3 - Transmitter Output Timing Jitter with Cable Model - Send 1500 Byte Packets containing Random data as the packet payload.

 

14.3.1.2.3 - Transmitter Output Timing Jitter without Cable Model - Send 1500 Byte Packets containing Random data as the packet payload.

 

 

IEEE 100Mbps Tests:

 

o Setup to be done before setting any patterns

 

o Write MDIO Phy Register 0x10, Turn off bit 10

 

o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3

 

o Write MAC Register 0xE14, Turn off bit 5

 

o Write MDIO Phy Register 0x0, Set value to 0xA000

 

 

9.1.2.2 - UTP Differential Output Voltage – Should see 112ns wide pulses

 

9.1.4 - Signal Amplitude Symmetry

 

9.1.6 - Rise/Fall Times

 

o Write MDIO Phy Register 0x1A, Turn on Bit 3

 

 

9.1.5 -Transmit Return Loss – Should see random idles data

 

9.1.9 - Transmit Jitter

 

9.2.2 - Receiver Return Loss

 

o Write MDIO Phy Register 0x1A, Set Value to 0x0

 

 

9.1.8 - Duty Cycle Distortion (DCD) – Should see 16ns pulses

 

o Write MDIO Phy Register 0x1A, Turn on bits 2 and 3

 

 

IEEE 1Gbps Tests

 

Setup for all patterns

 

o Write MDIO Phy Register 0x0, set value 0x9140 – This sets it to Gigabit and resets the adapter.

 

 

40.6.1.2.1 - Peak Differential Output Voltage (Test Mode 1)

 

40.6.1.2.2 - Maximum Output Droop (Test Mode 1)

 

o Write MDIO Phy Register 0x9, set value 0x3B00

 

 

40.6.1.2.4 - Transmitter Distortion (Test Mode 4)

 

40.8.3.1 - MDI Return Loss (Test Mode 4)

 

40.8.3.3 - MDI Common-Mode Output Voltage (Test Mode 4)

 

o Write MDIO Phy Register 0x9, Set value 0x9B00

 

 

40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 2)

 

o Write MDIO Phy Register 0x9, Set value 0x5B00

 

 

40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 3)

 

o Write MDIO Phy Register 0x9, Set value 0x7300

View solution in original post

25 Replies
CarlosAM_INTEL
Moderator
1,019 Views

Hello, Andrija :

Thank you for contacting Intel Embedded Community.

The information that may help you is stated in sections 3.7.8.1.2, 4.5.7.2.2, 4.5.7.2.3, 8.2.1, 8.17.2, 8.25.12, 8.27.3.1, 8.27.3.5, 8.27.3.15, and 8.27.3.30; Figure 3-16, and Table 10-21; on pages 115, 147, 378, 479, 480, 548, 553, 556, 557, 563, 114, and 673 of the https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/i210-ethernet-controller-dat... Intel(R) Ethernet Controller I210 Datasheet document # 333016.

We hope that this information may help you.

Best regards,

Carlos_A.

CLui1
Novice
1,019 Views

Hello Carlos,

I work also with the i210 component and I search to perform the ethernet compliant test to 10/100BASE-T too. I've just subscribe myself in when I saw your post.

I looked at the chapters you refered to in your reply, but it's still not clear to me how to enable a test mode pattern generation.

I found inside the datasheet "12.5.7 Physical Layer Conformance Testing" that for "Output Amplitude, Rise and Fall Time (10/100 Mb/s), Symmetry and Droop (1 GbE). For the I210,

use the appropriate PHY test waveform."

Where are the "test waveform" for the 10/100 Mb/s? it's not described inside this datasheet. Should we generate them outside of the component? there is only a Test mode for the 1000BASE-T, do the component have a similary mode for the speed lower?

I have another component on my product which use a TI PHY -DP38xx, and they have a document which explains how to configure the component for conformance testing, do you have something close to this document ? (http://www.ti.com/lit/an/snla239a/snla239a.pdf http://www.ti.com/lit/an/snla239a/snla239a.pdf )

For the testing tools we have a Teledyne/Lecroy automated Ethernet test suite on which we directly plug our DUT and run the conformance test.

Thanks for pointing me in the right direction.

Celine

AStoj1
New Contributor I
1,019 Views

Hi Celine

Thanks for your support.

You saved my day.

Andrija

CLui1
Novice
1,019 Views

Can someone help us on this subject please?

I tried to contact the support through the customer support and they closed my ticket by telling me to create another ticket from here :

https://www.intel.com/content/www/us/en/design/resource-design-center.html

Andrija and I are still waiting for a support on the compliance test topic!

Thanks....

Celine

CarlosAM_INTEL
Moderator
1,019 Views

Hello, celinel and Andrija :

Thanks for your reply.

We suggest you review as a reference the information stated at the following website:

ftp://ftp.qualitech.net/remotesupport/Drivers/LAN/Intel/Intel/TOOLS/DOCS/ieee%20gig%20tm.pdf

In case that you want an updated version of this information, we suggest you address your request by filling out the https://plan.seek.intel.com/us_en_embedded_registration-form-contactsaleswebform_html Embedded Design Assistance form.

We hope that this information may help you.

Best regards,

Carlos_A.

AStoj1
New Contributor I
1,019 Views

Hi Carlos

Thanks for the link.

Now we need the same document but for the I210-AT. Can't you provide us this document?

I wrote to your sales department through filling out the form you stated.

But I think this will take another month or more to get any information, you will be definitely faster.

Thanks

Andrija

CarlosAM_INTEL
Moderator
1,019 Views

Hello, Andrija :

Thanks for your reply.

Please let us clarify the propose of our communications.

The document mentioned in our last message is general for the Intel Ethernet Controllers.

By the way, the information provided on our first communication is specific for the cited device because we had the idea that the cited document has been reviewed by you.

Due to these facts, we suggest you use the procedure stated in the document listed in our previous interaction but using the information stated in our first message to have specific information for the device that you are using.

We hope that this may help you.

Best regards,

Carlos_A.

AStoj1
New Contributor I
1,019 Views

Hi Carlos

Thanks again for the documents.

In Appendix H of the last document there is a nice table about Manual Register Settings of your 82540/82546/82541/82547/82544 families.

I think that it would be great to have the same table for the I210-AT.

At the end you are also doing the same Ethernet Compliance Tests and have to set different registers for the different tests.

How do you test your I210-AT for compliance?

Thanks again for your help

Andrija

CarlosAM_INTEL
Moderator
1,019 Views

Hello, Andrija :

Thanks for your reply.

The https://cdrdv2.intel.com/v1/dl/getContent/348742 Intel(R) Network Connections Tools document # 348742 has the LANConf tool that may help you.

It is accessible when you are logged into your Resource & Design Center (RDC) privileged account. It can be requested by filling out the https://www.intel.com/content/www/us/en/forms/design/contact-support.html RDC Account Support form.

We hope that this information may help you.

Best regards,

Carlos_A.

AStoj1
New Contributor I
1,026 Views

IEEE 10Mbps Tests:

 

• Setup For All patterns – This needs to be done before sending packets with the listed payload below for each test. Ensures the link is forced up so packets will send and that no other 100/1G test modes are running.

 

o Write MDIO Phy Register 0x10, Turn off bit 10

 

o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3

 

o Write MAC Register 0xE14, Turn off bit 5

 

o Write MDIO Phy Register 0x10, Turn on bit 10

 

o Write MDIO Phy Register 0x16, Set value to 0x6

 

o Write MDIO Phy Register 0x10, Set Value to 0x0

 

o Write MDIO Phy Register 0x16, Set Value to 0x0

 

o Write MDIO Phy Register 0x0, Set Value to 0x0

 

14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 5MHz) – Send 1500 Byte Packets containing AA pattern as the packet payload.

 

14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 10MHz) - Send 1500 Byte Packets containing FF pattern as the packet payload.

 

14.3.1.2.1 - Harmonic Content, All Ones Signal - Send 1500 Byte Packets containing FF pattern as the packet payload.

 

14.3.1.2.1 - Differential Output Voltage Template - Send 1500 Byte Packets containing Random data as the packet payload.

 

14.3.1.2.1 - TP_IDL Waveform Output – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0.

 

14.2.1.4 - RD Circuit Differential Input Impedance (Rx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0.

 

14.3.1.2.2 - TD Circuit differential Output Impedance (Tx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0.

 

14.3.1.2.5 - TD Circuit Common-Mode Output Voltage - Send 512 Byte Packets containing Random data as the packet payload.

 

14.3.1.2.3 - Transmitter Output Timing Jitter with Cable Model - Send 1500 Byte Packets containing Random data as the packet payload.

 

14.3.1.2.3 - Transmitter Output Timing Jitter without Cable Model - Send 1500 Byte Packets containing Random data as the packet payload.

 

 

IEEE 100Mbps Tests:

 

o Setup to be done before setting any patterns

 

o Write MDIO Phy Register 0x10, Turn off bit 10

 

o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3

 

o Write MAC Register 0xE14, Turn off bit 5

 

o Write MDIO Phy Register 0x0, Set value to 0xA000

 

 

9.1.2.2 - UTP Differential Output Voltage – Should see 112ns wide pulses

 

9.1.4 - Signal Amplitude Symmetry

 

9.1.6 - Rise/Fall Times

 

o Write MDIO Phy Register 0x1A, Turn on Bit 3

 

 

9.1.5 -Transmit Return Loss – Should see random idles data

 

9.1.9 - Transmit Jitter

 

9.2.2 - Receiver Return Loss

 

o Write MDIO Phy Register 0x1A, Set Value to 0x0

 

 

9.1.8 - Duty Cycle Distortion (DCD) – Should see 16ns pulses

 

o Write MDIO Phy Register 0x1A, Turn on bits 2 and 3

 

 

IEEE 1Gbps Tests

 

Setup for all patterns

 

o Write MDIO Phy Register 0x0, set value 0x9140 – This sets it to Gigabit and resets the adapter.

 

 

40.6.1.2.1 - Peak Differential Output Voltage (Test Mode 1)

 

40.6.1.2.2 - Maximum Output Droop (Test Mode 1)

 

o Write MDIO Phy Register 0x9, set value 0x3B00

 

 

40.6.1.2.4 - Transmitter Distortion (Test Mode 4)

 

40.8.3.1 - MDI Return Loss (Test Mode 4)

 

40.8.3.3 - MDI Common-Mode Output Voltage (Test Mode 4)

 

o Write MDIO Phy Register 0x9, Set value 0x9B00

 

 

40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 2)

 

o Write MDIO Phy Register 0x9, Set value 0x5B00

 

 

40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 3)

 

o Write MDIO Phy Register 0x9, Set value 0x7300

View solution in original post

CarlosAM_INTEL
Moderator
1,019 Views

Hello, Andrija :

Thanks for your reply.

We are glad that you have found the proper information to solve this inconvenience since you consider your previous communication as the useful and correct answer.

Please do not hesitate to contact us if you have more questions related to Intel Embedded devices.

Best regards,

Carlos_A.

CLui1
Novice
1,019 Views

Hello Andrija,

I looked at the registers you described in the last post. As I don't have the access yet to the privileged access to read the document Carlos_A quoted, I have some question about the registers you mentioned.

If I undestand well, the MDIO PHY registers are the ones in the i210 datasheet §8.27.3. but I have some difficulties to find the equivalent registers.

Here is what I think it may corresponds to, can you tell me if this is correct?

10Mbps :

o Write MDIO Phy Register 0x10, Turn off bit 10 --> Page 0 Register 16, bit 10 to disable the copper link good

o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3 --> this one I cannot match with neither Page 6 Register 26 nor Page 26 Register 26

o Write MAC Register 0xE14, Turn off bit 5 --> PHPM register

o Write MDIO Phy Register 0x10, Turn on bit 10 --> Page 0 Register 16, bit 10 to force the copper link good

o Write MDIO Phy Register 0x16, Set value to 0x6 --> Page address Register 22 to set the page to 6

o Write MDIO Phy Register 0x10, Set Value to 0x0 --> page 6 Register 16 ? I did'nt understand why we set all bits to 0, there will be no packet generation for the test

o Write MDIO Phy Register 0x16, Set Value to 0x0 --> Page address Register 22 to set the page back to 0

o Write MDIO Phy Register 0x0, Set Value to 0x0 --> Page 0 Register 0, I am confused with value 0x0 because this will set the link to 10Mbps but in HALF duplex mode

Thank you for your help and the knowledge sharing.

Celine

CarlosAM_INTEL
Moderator
1,019 Views

Hello, celinel:

Unfortunately, Andrija is unavailable to help you.

Due to this fact, we suggest following the recommendation stated in our communication of the past June 5th, 2018.

By the way, please send your design to be verified by the https://edc.intel.com/Tools/Design-Review/Default.aspx?language=en&r=1244566572 Intel Schematic and Layout service .

We hope that this information may help you.

Best regards,

Carlos_A.

AStoj1
New Contributor I
1,019 Views

Hi Carlos

Fortunately, I helped her via personal email.

Best regards,

Andrija

CarlosAM_INTEL
Moderator
1,019 Views

Hello, Andrija:

Thanks for your update.

We are glad that you helped celinel because there was no answer through this channel.

It would be highly appreciated if you can share the information unrelated to the Intel CNDAs that you have sent to celinel via this thread.

Best regards,

Carlos_A.

AStoj1
New Contributor I
1,019 Views

Hi Carlos

I just wrote that it should work like that, nothing interesting for the community.

Bye

guelermus
Beginner
230 Views

Hi,

I need to acces the registers you have given
above from an ARM Linux platform.

The port is connected to the system over i210 on the PCI bus.
There is no direct MII connection to the compliance registers.
I think I have to use tools like devmem
or busybox devmem2 to access them.

Could you please explan how to acces to the registers
you listed above over PCI memory space?

Best,
Gueler

CarlosAM_INTEL
Moderator
226 Views

Hello, @guelermus:

Thank you for contacting Intel Embedded Community.

You should contact the manufacturers of the mentioned test tools to clarify the proper procedure to use the information provided in our previous communications. 

You can contact them as a reference to the channels listed on the following website:

https://github.com/brgl/busybox/issues

Best regards,

@CarlosAM_INTEL

guelermus
Beginner
220 Views

Hi Carlos,

Actually I dont have any problem with "busybox devmem" tool. My question is about accessing the registers given ( they are not direct PCI addresses) with any user space memory acess tool?

Should I sum them with the device base address and some offset?
For the given line "Write MDIO Phy Register 0x9, Set value 0x9B00", is it OK to say:
"sudo busybox devmem <base_address + some_offset + 0x9> 16 0x9B00" ???

Or do I need a more complex "indirect register addressing" mechanism to access those registers?

Best,
Gueler

CarlosAM_INTEL
Moderator
213 Views

Hello, @guelermus:

Thanks for your reply.

You should contact the manufacturer of the test tool that you would use to verify the way to use the information stated in sections 8.1.1.1, 8.1.1.5, 8.1.3.1, 8.6, and Table 8-6, on pages 361, 362, 363, 375, 377, and 405 through 411 of the Intel® Ethernet Controller I210 Datasheet document # 333016 that may answer your question. You can find it when you are logged into your Resource and Design Center (RDC) privileged account on the following website:

https://cdrdv2.intel.com/v1/dl/getContent/333016 

The RDC Account Support form is the channel to process your account update request or report any inconveniences with the provided website. It can be found at:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

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