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WBall
Beginner
705 Views

I210 JTAG mode

I am using the I210 in a design.  I am the designer,   there is no third party.  My question is about JTAG mode on the I210 part.  On many parts, there is a pin that allows you to be in or out of JTAG mode.  Is there such a pin on the I210 part?  Also on the I210  reference schematics,  sheet 5,  I see the following 3 lines that reference JTAG: 

NVM_SK=JTAG Mode

JTAG_MAIN->PU(INT)

JTAG_RSVD->PD (R20)

Please explain what the above 3 lines mean.  This information is not in the datasheet.    For instance how does the NVM_SK pin equal (=) JTAG mode?  In the data sheet, the  NVM_SK is defined as  the  non volatile  serial clock output.  Nothing is mentioned about the NVM_SK pin having anything to do with JTAG.

Thank you

Whitney Ballard

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6 Replies
CarlosAM_INTEL
Moderator
321 Views

Hello, @WBall​ :

 

Thank you for contacting Intel Embedded Community.

 

In order to set the mentioned mode TDI, TDO, TMS, and CLK should all be pulled high with 3.3kΩ resistors.

 

Best regards,

@Mæcenas_INTEL​.

WBall
Beginner
321 Views

I question whether 3.3K ohm  pull up resisters on the JTAG signals  will put the I210 part in JTAG mode.   ​In general if a part is in JTAG mode (in this case the I210)  it will not function normally.  So once we attach 3.3K pull up resisters to the JTAG lines,  per your answer,  if true,  the part will be in JTAG mode and  it will not function as a Etherent controller.   Page 5 of the I210 referecne schematic has these pull up resisters so how would the part function if these resisters held the part in JTAG mode?   

I have done a little more research.   One the the JTAG signals is TRST_N which when asserted to logic low,  will hold the JTAG interface in reset,  allowing the part to function normally.  It is essentially the JTAG interface reset signal.    This signal is optional however per the JTAG standard.    Does the I210 have such a pin (maybe a multi functional pin) that is not labeled with TRST_N.

My concern is that when I see  the following 3  lines  on  page 5 of the I210 reference schematic,  there is some feature that is not documented that I need to know about.

NVM_SK=JTAG Mode

JTAG_MAIN->PU(INT)

JTAG_RSVD->PD (R20)

What does NVM_SK have to do with JTAG Mode?   Also R20 is a provisional pull down resister on the NVM_SK line.   Why is it there? 

On page 10 of the I210 reference schematic,  there is a JTAG Test Interface connector labelled J20.  One of the signals on it is JRST_N.    This would appear to be the JTAG TRST_N signal but it is not connected to any circuitry.    Was it supposed to be connected to a pin on the I210 part?

Thank you

Whitney Ballard

 

CarlosAM_INTEL
Moderator
321 Views

Hello, @WBall​:

 

Thanks for your reply.

 

It is important to let you know that NVM_SK is the serial clock for the flash chip.

 

We suggest you review the information related to the pins mentioned in our previous communication and JTAG usage. It is stated in Table 2-1, and sections 12.11, and 14; on pages 23, 840, 841, 842, 849, and 850 of the Intel(R) Ethernet Controller I210 Datasheet document # 333016 that can be found at:

 

https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/i210-ethernet-controller-dat...

 

Best regards,

@Mæcenas_INTEL​.

WBall
Beginner
321 Views

​The last reply does not answer my question.  Why do the reference schematics  for the Intel I210 part  have a provisional pull down resister (R20)  on the NVM_SK (clock) lines with the following notes

NVM_SK=JTAG Mode

JTAG_MAIN->PU(INT)

JTAG_RSVD->PD (R20)

The data sheet has no reference to this.    it would appear that the NVM_SK signal is being used as a strap input signal maybe  at power up but no explanation is given in the data sheet.  Is it possible to escalate  this question to someone else?

Thank you

Whitney Ballard

CarlosAM_INTEL
Moderator
321 Views

Hello, @WBall​:

 

Thank you for contacting Intel Embedded Community.

 

Adding a PD to NVM_SK puts the i210 device into an Intel reserved JTAG mode.

 

There is no JTAG reset pin on the i210.

 

Please disregard the PD option for NVM_SK.

 

Please let us know if you have any update or question related to this.

 

Best regards,

@Mæcenas_INTEL​.

NDeLa2
Beginner
221 Views

Hi @WBall , I realize this may not be helpful to you at this point, but I recently came across issues using JTAG with the i210 chip. Through another forum post on here, someone else discovered that the LAN_PWR_GOOD pin must be held low in order to enable JTAG mode. This is opposite of what the reference design shows, and what BSDLs for other intel eth phys show (like 82580 where LAN_PWR_GOOD must be held high for JTAG mode). Holding LAN_PWR_GOOD low holds the chip in reset, which apparently also enables JTAG test mode - this is not documented anywhere. Posting this so others who try in the future can have quicker success and/or save themselves a board re-spin.

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