We are making a PCB with (2) i210 ethernet controllers, each on their own PCIe lane, routed back to a single E3950 single-board computer. Briefly, our question concerns which manufacturing flash image to pre-program to the i210 flash such that both PHY work in a separate clock configuration.
We are not using the reference/hint clock provided by the E3950 and instead are using an oscillator routed into a divider provided to both i210 PHY on our board. This is known as separate clock configuration, as opposed to common clock configuration if we were feeding the E3950 clock to the PHY (where the clock phase would be synchronous). In our separate clock configuration, the reference/hint clock we are providing to the i210 is asynchronous to the E3950.
In our testing, we found we could bring up one i210 at a time if we reworked our board in a common clock configuration. To do this, we jumpered the E3950 ref.clock straight to each i210. Before placing in-system, we flashed an 8Mb flash with Dev_Start_I210_Copper_SMB_8Mb_A2_3.25_0.03.hex on a flash programmer. Once everything was soldered onto our PCB and booted into Linux, we can see the i210 in lanconf and eeupdate tools and are able to program the i210 internal NVM with MAC address, etc. To get the 2nd i210 working, we re-soldered the E3950 ref. clock to that i210 to provide it a clock common to the E3950.
The issue we are having though is related to the separate clock configuration. Now with each PHY working on it's own, we break the trace from the E3950 ref.clock to our i210 and now insert our oscillator (putting the board into separate clock configuration) so it's routed to both i210. We can now see (2) i210 on the PCIe bus both with an ID=1531 (unprogrammed flash). But we are not able to talk to them with Intel tools such as lanconf and eeupdate. They do not appear at all in that tool.
Our suspicion is we need to pre-program the i210 flash with a different image that supports separate clock configuration. Does such an image exist?
Thank you for contacting Intel Embedded Community.
In order to be on the same page, could you please inform the sources that you have used to develop the design related to this thread?
By the way, could you please clarify if the project related to this forum has been reviewed by Intel?
We are waiting for your answers to your questions.
Our design was based off the Intel i210 reference design ("i210-at-i211-at-1g-base-t-reference-design-schematic.pdf") referencing the "i210-ethernet-controller-datasheet.pdf" datasheet. This design was not reviewed by Intel.
Thanks for your reply.
We suggest you sent your design to be verified by Intel following the procedure stated in the following website: