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Hi Support,
I am currently designing a board using Intel X710-BM2 to connect LSI and CPU with 10GBASE-KR.
How many lanes of PCIe should be connected in Gen2 to maximize the performance of the 10GBASE-KR*1port between the CPU and the X710-BM2?
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Hello, @yousuke:
Thank you for contacting Intel Embedded Community.
We sent an email to the address related to this account with information that may help you.
Best regards,
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Hello, @yousuke:
Thank you for contacting Intel Embedded Community.
We sent an email to the address related to this account with information that may help you.
Best regards,

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