xl710 add VEB/VEPA

[migo_gong]

Hello，I want to add veb/vepa and vsi through commands on the pv of xl710.But i am having some problems adding veb and vsi.

I can correctly add floating VEBs. But an error occurred while adding VEB with uplink and downlink.Appear “AQ command send failed Opcode 230 AQ Error:14    AQ desc WB 0x0007 0x0230 0x0000 0x000e 0x00000000 0x00000000 0x01860002 0x00ff0003 0x00000000 0x000b0000”

Secondly I also got error while adding vsi.

I put more detailed information in the attachment.

[Diego_INTEL]

Hello @migo_gong,

Thank you for contacting Intel Embedded Community.

Could you please clarify if this request is related to the Intel® Ethernet Controller XL710 design developed by you, or is a Network Interface Card (NIC) or add-in card developed by a third-party company?

Could you please let us know the name of the manufacturer, the part number, and where we can find the information on this device if it is a third-party design?

Can you check the most recent drivers for the Intel® Ethernet Controller XL710:

https://www.intel.com/content/www/us/en/download/18026/intel-network-adapter-driver-for-pcie-40-gigabit-ethernet-network-connections-under-linux.html

Best regards,

@Diego_INTEL 

[migo_gong]

Thank you very much for your response.

I am a student of network engineering, currently learning to use the features of xl710. While working with it, I came up with a simple idea to create a graphical interface in Linux. I have reviewed the data manual and the i40e code, but I haven't been able to utilize the basic functionalities yet. The main difficulty lies in the issue I mentioned in the attachment. This problem has been bothering me for a while, and I haven't been able to solve it. Therefore, I would like to seek the guidance of an Intel professional engineer.

I sincerely hope that you can help me resolve this issue, and I truly appreciate your assistance.

[migo_gong]

Hello, if you see this, could you please reply?

[Diego_INTEL]

Hello @migo_gong,

My apologies, I had this pending but being busy, I think the issue might be in incompatibility from driver and firmware, you can try to update the firmware of the controller to the latest and use the latest driver and then try again.

You may check this document for compatibilities between driver and firmware versions:

https://www.intel.com/content/www/us/en/content-details/332191/intel-ethernet-controller-x710-xxv710-xl710-feature-support-matrix.html?wapkw=332191&DocID=332191

Driver i40e. I think you are using igb, is okay but the version should match the document of compatibilities.

https://www.intel.com/content/www/us/en/download/18026/intel-network-adapter-driver-for-pcie-40-gigabit-ethernet-network-connections-under-linux.html

You can try to update the NVM with this document but you must be very careful.

https://www.intel.com/content/www/us/en/download/15084/intel-ethernet-adapter-complete-driver-pack.html

Best regards,

@Diego_INTEL 

[migo_gong]

Hello, the firmware update download page I found is shown in Image1, but you provided Image 2. Is there any difference between these two?

I should update which one?

[Diego_INTEL]

Hello @migo_gong,

I have shared you the one of ~700 Mb, include many images, use the one of your controller:

"You can try to update the NVM with this document but you must be very careful.

https://www.intel.com/content/www/us/en/download/15084/intel-ethernet-adapter-complete-driver-pack.html"

What is the second one from?

Also, you can use this as a tutorial:

Intel® Ethernet NVM Update Tool Quick Usage Guide for Linux

https://www.intel.com/content/www/us/en/content-details/332161/intel-ethernet-nvm-update-tool-quick-usage-guide-for-linux.html?wapkw=nvm%20update&DocID=332161

Best regards,

@Diego_INTEL 

[migo_gong]

"Thank you for taking the time to reply. :

I have already updated to the latest version.

Below is the command code I entered and the error feedback received.

（1）code

#include <stdio.h>

#include <stdlib.h>

#define __le16 unsigned short int

#define u8 char

#define __le32 unsigned long int

struct i40e_aqc_vsi_properties_data {

/* first 96 byte are written by SW */

__le16 valid_sections;

#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001

#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002

#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004

#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008

#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010

#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020

#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040

#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080

#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100

#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200

/* switch section */

__le16 switch_id; /* 12bit id combined with flags below */

#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000

#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)

#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000

#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000

#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000

u8 sw_reserved[2];

/* security section */

u8 sec_flags;

#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01

#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02

#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04

u8 sec_reserved;

/* VLAN section */

__le16 pvid; /* VLANS include priority bits */

__le16 fcoe_pvid;

u8 port_vlan_flags;

#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00

#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \

I40E_AQ_VSI_PVLAN_MODE_SHIFT)

#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01

#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02

#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03

#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04

#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03

#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \

I40E_AQ_VSI_PVLAN_EMOD_SHIFT)

#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0

#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08

#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10

#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18

u8 pvlan_reserved[3];

/* ingress egress up sections */

__le32 ingress_table; /* bitmap, 3 bits per up */

#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0

#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3

#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6

#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9

#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12

#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15

#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18

#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)

#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21

#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \

I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)

__le32 egress_table;   /* same defines as for ingress table */

/* cascaded PV section */

__le16 cas_pv_tag;

u8 cas_pv_flags;

#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00

#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \

I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)

#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00

#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01

#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02

#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10

#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20

#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40

u8 cas_pv_reserved;

/* queue mapping section */

__le16 mapping_flags;

#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0

#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1

__le16 queue_mapping[16];

#define I40E_AQ_VSI_QUEUE_SHIFT 0x0

#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)

__le16 tc_mapping[8];

#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0

#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \

I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)

#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9

#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \

I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)

/* queueing option section */

u8 queueing_opt_flags;

#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04

#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08

#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10

#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20

#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00

#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40

u8 queueing_opt_reserved[3];

/* scheduler section */

u8 up_enable_bits;

u8 sched_reserved;

/* outer up section */

__le32 outer_up_table; /* same structure and defines as ingress tbl */

u8 cmd_reserved[8];

/* last 32 bytes are written by FW */

__le16 qs_handle[8];

#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF

unsigned short int stat_counter_idx;

__le16 sched_id;

u8 resp_reserved[12];

};

int main()

{

    char buffer[256] = {0};

    int i=0;

    // Add vsi command

    struct i40e_aqc_vsi_properties_data cmdbuffer;

    cmdbuffer.valid_sections=0x00cf;

    cmdbuffer.switch_id=0;

   // cmdbuffer.sw_reserved=0;

    cmdbuffer.sec_flags=I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD;

    cmdbuffer.sec_reserved=0;

    //icmdbuffer.pvid=

    //cmdbuffer.fcoe_pvid=

    cmdbuffer.port_vlan_flags=0x00;

    //cmdbuffer.pvlan_reserved={0};

    cmdbuffer.ingress_table=0;

    cmdbuffer.egress_table=0;

    cmdbuffer.cas_pv_tag=0;

    cmdbuffer.cas_pv_flags=0x00;

    cmdbuffer.cas_pv_reserved=0;

    cmdbuffer.mapping_flags=1;

    //cmdbuffer.queue_mapping

    // cmdbuffer.tc_mapping

    cmdbuffer.queueing_opt_flags=0x04;

    // cmdbuffer.queueing_opt_reserved

    cmdbuffer.up_enable_bits=0;

    cmdbuffer.sched_reserved=0;

    cmdbuffer.outer_up_table=0;

    // cmdbuffer.cmd_reserved

    // cmdbuffer.qs_handle

    cmdbuffer.stat_counter_idx=0;

    cmdbuffer.sched_id=0;

    // cmdbuffer.resp_reserved=

    unsigned long buffer_address = (unsigned long)&(cmdbuffer.valid_sections);

    char high_address[16];

    char low_address[16];

    sprintf(high_address, "%08x", (unsigned int)((buffer_address >> 32) & 0xffffffff));

    sprintf(low_address, "%08x", (unsigned int)(buffer_address & 0xffffffff));

    printf("Buffer address: %lx\n", buffer_address);

    printf("High address: %s\n", high_address);

    printf("Low address: %s\n", low_address);

    printf("size: %d\n", sizeof(cmdbuffer));

sprintf(buffer, "echo send indirect aq_cmd 0 0x0210 0x80 0 0 0 0x000100a0 0x00060000 0x%s 0x%s 0x80 > /sys/kernel/debug/i40e/0000:61:00.0/command",high_address, low_address);

    int status = system(buffer);

    if (status == -1) {

        perror("system");

        exit(EXIT_FAILURE);

    }

    if (WIFEXITED(status)) {

        printf("Command exited with status %d\n", WEXITSTATUS(status));

    } else {

        printf("Command terminated abnormally\n");

    }

    printf("Press any key to continue.\n");

    getchar();

    return 0;

}

（2）Error feedback：

My driver version is the latest 2.22.18. However, while examining the command issuing process, I noticed that the driver does not handle the high and low addresses provided in my command. Can you confirm if the address of the command buffer provided in section 7.4.9.5.5.1 of the datasheet for the 'add vsi' command is the address that needs to be provided in the command? If it is, where does the driver handle it? I haven't seen any relevant processing except for the initial allocation of a buffer with a specified length (buff), but buff is not the address I provided for the command buffer. Moreover, the driver still sends this empty buff to the DMA."