Baytrail PCH-SMBus Modify Clock Frequency

[HS1]

Hi,

We created a BSP for custom Baytrail platform based on yocto dizzy release of valleyisland device. The Linux SMBus driver for Baytrail platform operates by default at 100 kHz. We are required to connect an device of 60 KHz.

As per atom e3800 datasheet, SMBus can be operated at speeds ranging from 10 kHz to 100 kHz. But I am not sure how to configure the SMBUS to operate on 60 kHz.

Can you please guide me

[Marcelo_M_Intel]

Hello hazzel,

Welcome to the Intel Embedded Community.

We are checking your case and we will contact you as soon as possible.

Regards,

Marcelo Montero

[Marcelo_M_Intel · Accepted solution]

Hello hazzel,

The SMBus frequency (FSMB) maximum and minimum values ( refer to page 58 ) depends of a clock synchronization mechanism to allow devices of different speeds to co-exist on the same bus. Due to this fact, the FSMB is defined by the devices connected to this bus.

You can read more about the SMBus 2.0 as a reference here http://www.smbus.org/specs/smbus20.pdf System Management Bus (SMBus) Specification.

The Intel(R) Atom(TM) Processor E3800 System Management Bus (SMBus) controller is compatible with the SMBus Specification Version 2.0.

You can confirm this in section 33, on page 4429 of the Intel(R) Atom(TM) Processor E3800 Family Datasheet document # 538136 version 3.6 that can be found at the following web site:

https://www-ssl.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html https://www-ssl.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html

Our suggestion in case that you have an issue with SMBus peripherals is to put additional delay to read/write properly.

On the other hand, in order to further help you with your driver and solution implementation please contact Yocto Project as is stated on page 3 of the Intel(R) Atom(TM) Processor E3800 Product Family Platform Brief that can be found at the following web site:

https://www-ssl.intel.com/content/dam/www/public/us/en/documents/platform-briefs/atom-processor-e3800-platform-brief.pdf https://www-ssl.intel.com/content/dam/www/public/us/en/documents/platform-briefs/atom-processor-e3800-platform-brief.pdf

Please tell me if you need anything else.

Best regards,

Marcelo

[HS1]

Hi MarceloMontero,

Thanks for the quick reply.

We had similar issues with an Intel Atom chipset with US15W System Controller Hub. We resolved this by setting SMBus to a lower frequency via HCLK—Host Clock Divider Register

We dont find an similar register with Intel Atom E3800 platform PCU-SMBus Controller. Can you please let me know how to modify SMBus frequency via registers?

[Gabriel_T_Intel]

Hello Hazzel,

We are checking your case and we will contact you with additional information as soon as possible.

Thanks,

Gabriel Thomas

[idata]

Hello hazzel,

Thanks for your update.

Our suggestion in case that you have an issue with SMBus peripherals, is putting additional delays to read/write properly, since a register

solution is unavailable for Bay trail -I.

Please let me know if this answers your consultation.

Best regards,

Jimmy.

[HS1]

Will try and let you know if this solves the issue

[HS1]

Hi,

would you please clarify "putting additional delays to read/write properly"?

Is that suggestion implies a resolution in software; ie. Software driver adding delay to read/write operation?

This would suggests that the SMBus driver on the Bay Trail is bit bang controlling every clock transition; instead of a hardware controller inside the Bay Trail SoC. '

Also please clarify the use of

SMBUS_PIN_CTL Register (SMB_Mem_SMBC)—Offset Fh

Bit 2 SMBCLKCTL

Is that in anyway related to clock stretching capability of SMBus

Thanks

[idata]

Hello hazzel,

Correct, our suggestion to put additional delays to read/write is accomplished through software.

Based on the description stated in section 33.7.11, on page 4462 of the Intel® Atom™ Processor E3800 Product Family Datasheet (doc# 538136) the SMBCLKCTL bit is related to the SMB_CLK pin status, which is unrelated to clock stretching capabilities on the SMBus.

Regards,

Jimmy.

[HS1]

Below is a reference from SMBus v2.0 specification

Can you please let me know if there is any way by which the Baytrail SMBus controller can extend SMBus clock low period?

[Gabriel_T_Intel]

Hello Hazzel,

We are checking this out for you, please stay tuned!

Regards,

Gabriel Thomas

[idata]

Hello hazzel,

We're investigating this, as soon as we have an update we'll write back.

Regards,

Jimmy.

[idata]

Hi Hazzel,

Just wanted to let you know we are still working with our engineers with this, please stay tuned for more updates.

Thanks!

[idata]

Hello hazzel,

We have corroborated with our engineers that there's no way to alter the SMBus frequency by using registers on this processor. The method that's used in order to achieve this, is as we have stated before, by adding read/write delays through software.

Clock stretching is negotiated between the SMBus controller and the peripherals. Therefore it's not recommended to alter the SMBus frequency since this would interfere with the negotiations.

As you're trying to use a device with a frequency of 60kHz, that falls in the range of the SMBus specification (10-100 kHz). There shouldn't be an issue when interfacing with this device through the SMBus.

As your platform supports yocto dizzy our best recommendation is to contact them by mail or on their forums, to verify if the clock stretching capability has been implemented:

https://www.yoctoproject.org/questions https://www.yoctoproject.org/questions

Additionally as a reference, you can check this link to a driver implementation:

http://lxr.free-electrons.com/source/drivers/i2c/busses/i2c-isch.c Linux/drivers/i2c/busses/i2c-isch.c - Linux Cross Reference - Free Electrons

Hope this helps. Please let us know if you have any other inquire.

Best regards,

Jimmy.

[Gabriel_T_Intel]

Hello Hazzel,

We have corroborated with our engineers that there's no way to alter the SMBus frequency by using registers on this processor. The method that's used in order to achieve this, is as we have stated before, by adding read/write delays through software.

Clock stretching is negotiated between the SMBus controller and the peripherals. Therefore it's not recommended to alter the SMBus frequency since this would interfere with the negotiations.

As you're trying to use a device with a frequency of 60 kHz, that falls in the range of the SMBus specification (10-100 kHz). There shouldn't be an issue when interfacing with this device through the SMBus.

As your platform supports yocto dizzy our best recommendation is to contact them by mail or on their forums, to verify if the clock stretching capability has been implemented:

https://www.yoctoproject.org/questions https://www.yoctoproject.org/questions

Additionally as a reference, you can check this link to a driver implementation:

http://lxr.free-electrons.com/source/drivers/i2c/busses/i2c-isch.c Linux/drivers/i2c/busses/i2c-isch.c - Linux Cross Reference - Free Electrons

Hope this helps. Please let us know if you have any other inquire.

Best Regards,

Gabriel Thomas