Braswell PLTRST# problem

[KChen86]

Hi,

There is a issue about PLTRST# . The platform is Braswell N3010 and TI PMIC (TPS650842). I do the power up without BIOS code, the power sequence seems to be good, but PLTRST# can't rise up after the VCCAPWROK & COREPWROK asserted by PMIC, and lpc_clkout0 is low. Then i check the 19.2MHz crystal. I removed the C1&C2(both 18pF), and used the scope probe touch the OSCIN & OSCOUT pin several times, after that lpc_clkout0 outputs 19.2MHz clock wave at 3.3V amplitude and the PLTRST# rise up! I reproduced this phenomenon 5-10 times, the number of probe touch times is different, it's hard to reproduce. What's the issue?

the attached file is 19.2MHz OSCIN&OSCOUT scope shot.

OSCIN:

OSCOUT:

Thanks,

KEVIN

[CarlosAM_INTEL]

Hello KevinChen29 ,

Thank you for contacting the Intel Embedded Community.

The information that may help you is stated in the http://www.intel.com/content/dam/doc/application-note/ich-family-real-time-clock-accuracy-considerations-note.pdf AP-728 Intel(R) I/O Controller Hub [Intel(R) ICH] / Platform Controller Hub (PCH) Family Real Time Clock (RTC) Electrical, Mechanical, and Thermal Specification (EMTS) .

It is important to clarify you that any situations out of the stated in the Intel documentation should be tested and validated by the manufacturers of the designs under these conditions.

Intel guarantees the proper functionality of their devices if the guidelines stated in the documentations are followed.

By the way, it seems that this forum is similar to the Braswell N3010 power sequence problem, if it is correct, could you please tell us if you have followed our suggestions?

We hope that this information is useful to you.

Best Regards,

Carlos_A.

[KChen86]

Hi Carlos,

The information that you provided is about RTC, but I think the issue is about the main clock 19.2MHz or iclk module. The LPC_clkout0 should output 25MHz clock, not 19.2MHz. What can be a cause? Why PLTRST# still low after PWROK is asserted by PMIC.

Thanks,

Kevin

[CarlosAM_INTEL]

Hello KevinChen29,

Thanks for your clarification.

We suggest you verify that your design has implemented the guidelines stated in the description column of the Table 4-1, on page 53 of thehttp://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-datasheet-vol-1.pdf N-series Intel(R) Pentium(R) Processors and Intel(R) Celeron(R) Processors: Datasheet—Volume 1 of 3 document # 332092; and LPC Control register bits 0 and 1 information stated in section 33.18.52, on page 2305 of thehttp://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-datasheet-vol-3-2015.pdf N-series Intel(R) Pentium(R) Processors and Intel(R) Celeron(R) Processors: Datasheet—Volume 3 of 3 document # 332094.

By the way, in order to may solve this and the forum listed on my previous communication, please review with the asistance of your BIOS developer the information stated on pages 27 and 28 of the Braswell System-on-Chip (SoC) BIOS Writers Guide (BWG) document # 541233.

We hope that this information may help you.

Best Regards,

Carlos_A.

[KChen86]

Hi Carlos,

I see the LPC clkout0 can output 19.2MHz or 25MHz stated in the document # 332092, but there is only 25MHz stated in the document # 547869(published in Feburary 2015).

The main issue is the PLTRST# can't rise up after PWROK asserted by PMIC. The power sequence seems to be good, and there is no BIOS code when i do the power up, the PLTRST# must rise up before CPU fetching the BIOS code. The LPC _clkout0 is no output. After several touches in 19.2MHz crystal OSCIN by the scope probe, the LPC_clkout0 outputs 19.2MHz clock wave,and PLTRST# rise up. What can be a cause? The iclk PLL didn't catch the 19.2MHz crystal wave? The oscillation amplitude is not enough?

Thanks,

KevinChen

[CarlosAM_INTEL]

Hello KevinChen29 ,

Thanks for your update.

Reviewing the Tables 4-1 and 4-2 on page 63 of the https://www-ssl.intel.com/content/www/us/en/secure/embedded/nda/products/braswell/n-series-pentium-celeron-processors-eds-vol-1.html N-series Intel(R) Pentium(R) Processors and Intel(R) Celeron(R) Processors External Design Specification (EDS) – Volume 1 of 3 document # 547869 [Rev 2.2 v1 of February 2016] confirms the information provided in our previous communication is correct.

By the way, in order to better help you with your consultations of your implementation, we suggest you filling out the https://www-ssl.intel.com/content/www/us/en/secure/forms/design-assistance.html Request Design Assistance Form and address your questions through this channel because you have omitted some of our previous suggestions.

We hope that this information may help you.

Best Regards,

Carlos_A .

[KChen86]

Hi Carlos,

The information that you provided is correct,Thanks for you help! But it's not key to the issue. I still can't find the reason which cause the issue. The LPC_clkout0 didn't output 19.2MHz clock wave means the iclk PLL didn't work?

I have filled out the Form.

Thanks,

Kevin

[CarlosAM_INTEL]

Hello KevinChen29 ,

Thanks for your update.

We are glad to hear that this consultation has been addressed to the Design Assitance channel. By the way, could you please verify if the LPC_clkout1 can operate at 19.2 MHz following our previous suggestions?

Thanks in advance for your reply.

Best Regards,

Carlos_A.

[KChen86]

Hi Carlos,

We didn't use LPC_clkout1, so we left it as NC. I can't verify if LPC_clkout1 can output 19.2MHz. After PWROK asserted by PMIC, the PLTRST# can't rise up, what can be a cause? Only power sequence and clock circuit can cause this issue?

Thanks,

Kevin

[MHuan40]

Hi Kevin,

You might have to enable or choose right setting value to enable LPC_clkout1 by softstrap via Flash_Image_Tool (FIT) in Braswell TXE FW package if you would like to check LPC_clkout1... you need to get the help from your BIOS team...

PS. I'm a BIOS engineer.

Best Regards,

Morgan Huang

[KChen86]

Hi Morgan,

I can't to ask for help from our BIOS team, because this issue seems to be a hardware issue. I just do the test without BIOS code. The PLTRST# should rise up before CPU begin fetching the BIOS code. The main issue isn't the LPC_clkout0 can't output 19.2MHz, it's the PLTRST# didn't rise up after the corepwrok & vccapwrok is asserted by PMIC. I check the power sequence, it seems to be right as the EDS stated. Then i check the 19.2MHz crystal, i used the scope probe touch the OSCIN pin several times, after that lpc_clkout0 outputs 19.2MHz clock wave(lpc_clkout0 output is low before i touch the OSCIN pin) and the PLTRST# rise up! I guess it's something about iclk or 19.2MHz crystal goes wrong. I adjusted the crystal's matching capacitor C1&C2 and replace a new crystal, there is no improvement. What can be a cause?

Thanks,

Kevin

[CarlosAM_INTEL]

Hello KevinChen29 ,

Thanks for your update.

The MorganHuang 's suggestion should be considered from your side, because the BIOS is an important factor that could cause this situation.

By the way, please try to implement our last suggestion and let us know the results as soon as you have it.

Thanks again for your help to solve this inconvenience.

Best Regards,

Carlos_A.

[KChen86 · Accepted solution]

Hi Carlos,

OK, i don't know do you understand what i said previous.

The first, you say BIOS can cause this situation. But in 5.2.3 on page 72 of the document # 547869 [Rev 1.5]. Before CPU fetching BIOS code, the PLTRST# should de-asserted.

Second, you last suggestion is verify if the LPC_clkout1 can operate at 19.2 MHz. I already answer you that the LPC_clkout1 is NC status in our board, there is no test point, i can't verify it.

Third, Do you pay a attention to my issue? Or do you understand what i said? The Intel support is such things like this? I ask the CCE(ccechina.intel.com) for help, they say they know nothing about this issue,and you must do as the PDG or CRB. Then i want to ask this community for help, OK, the result is terrible.

Thanks for all your help!

[MHuan40]

Hi Kevin,

I understood... Since the PLTRST# rise up after your probe touched, is there possible of the level of logic voltage (either level-trigger or edge-trigger) of somewhere the resistance of board circuit affects doesn't meet the spec (Figure 5-2, platform Power Up Sequence) ? Sorry~ Just my guess...

Best Regards,

Morgan Huang

[KChen86]

Hi Morgan,

I checked the power sequence and compared the result with Figure 5-2, platform Power Up Sequence. It's seems to be right. I guess crystal circuit or clock module goes wrong. Then i found the LPC_clkout0 is 0 (it should output 19.2MHz square wave before PLTRST# de-asserted). It looks like the 19.2MHz crystal or PLL of CPU goes wrong. But the OSCOUT of 19.2MHz crystal outputs 19.2MHz sine wave, it means 19.2MHz crystal have already oscillate. So i think maybe PLL or something in iclk module isn't working. I want to ask for help in this community because there is no information about PLL or iclk module. you know what i mean?

Thanks,

Kevin

[CarlosAM_INTEL]

Hello KevinChen29 ,

Please let us explain the reasons to our previous suggestions.

In our communication of the past July 27th, 2016 8:35 AM, we clearly suggested verifying the BIOS Writers Guide with the assistance of your BIOS developer, because there are some requirements related to the signal related to your consultation. It is important to let you know that this document is accessible to the EDC privileged account owners.

Our suggestion to test the LPC_clkout1 signal at 19.2 MHz was made to verify the proper functionality of the Braswell devices affected by this situation.

On the other hand, reviewing your last communications and in order to better understand this situation, we would like to address the following questions:

Could you clarify us if this situation happens with your design or with a Customer Reference Board (CRB)? How many units are affected? In case that this issue is related to your design, could you please reproduce this issue in a CRB, and let us know the consequences?

In case that your design is the related to this situation, could you please confirm that the LPC guidelines have been implemented on it? This information is stated in section 16, on pages from 143 to 147 of the https://www-ssl.intel.com/content/www/us/en/secure/embedded/nda/products/braswell/pentium-celeron-n3000-design-guide.html Intel(R) Pentium(R) and Celeron(R) Processors N3000 Platform Design Guide (PDG) document # 540602 that should be accessible to you if you have an EDC privileged account.

Please give us all the information requested through the previous questions to better understand your consultation.

Thanks in advance for your help with this.

Best Regards,

Carlos_A.

[KChen86]

Hi Carlos,

you still didn't understand what i say.

First, this issue has nothing to do with BIOS, and LPC isn't the cause of issue,it's result of the issue.

You always let me check the LPC and BIOS. Could you pay more attention to this issue itself? It's a issue about PLTRST# can't rise up after power up. It's not a LPC issue!!

This situation happens with our design. And i don't have a CRB board. I can't reproduce this issue in CRB. 4 of 4 our boards have this issue.

Is this community have any Application engineer or hardware engineer of Intel?

Thanks,

Kevin

[CarlosAM_INTEL]

Hello KevinChen29 ,

Thanks for your clarification.

The further help at this point should be the one from the Design Assistance team, which has been contacted by you as is stated in your communication of the past July 29th, 2016 specifically at 1:03 AM.

Please wait for their answer.

Best Regards,

Carlos_A.

[CarlosAM_INTEL]

Hello ,

Thanks for your clarification.

The further help at this point should be the one from the Design Assistance team, which has been contacted by you as is stated in your communication of the past July 29th, 2016 specifically at 1:03 AM.

Please wait for their answer.

Best Regards,

.

[scoll1]

Dear Carlos,

I am stuck with the same issue. What are the signals and conditions to check on the board itself to get the Braswell (a N3160) to deassert PMC_PLT_RST# after PMC_CORE_PWROK is asserted? I have verified with great care the power up sequence from G3 to S0. Everything is OK, voltage and timings as in figure 5-2 of the datasheet, also RTC and 19.2MHz Oscillators are perfectly stable. I can see the SUSCLK running but not the LPCCLK0.

As Kevin, I confirm this issue is before executing the BIOS, so it is hardware related only and no sotfware is involved.

I can not find enough information from Intel's CRB (Cherry Hill) and PDG so would it be possible to be contacted by your assistance team?

Best Regards,

Sam

[B-OatPQURE]

So long time without getting a proper answer! The Trusted Execution Engine (TXE) cpu holds PLTRST# inactive as an empty flash does not fulfill the requirements for starting the BSP.