Solved: Braswell PLTRST# problem - Page 2

KChen86 · ‎07-24-2016

Hi,

There is a issue about PLTRST# . The platform is Braswell N3010 and TI PMIC (TPS650842). I do the power up without BIOS code, the power sequence seems to be good, but PLTRST# can't rise up after the VCCAPWROK & COREPWROK asserted by PMIC, and lpc_clkout0 is low. Then i check the 19.2MHz crystal. I removed the C1&C2(both 18pF), and used the scope probe touch the OSCIN & OSCOUT pin several times, after that lpc_clkout0 outputs 19.2MHz clock wave at 3.3V amplitude and the PLTRST# rise up! I reproduced this phenomenon 5-10 times, the number of probe touch times is different, it's hard to reproduce. What's the issue?

the attached file is 19.2MHz OSCIN&OSCOUT scope shot.

OSCIN:

OSCOUT:

Thanks,

KEVIN

KChen86 · ‎08-01-2016

Hi Carlos,

OK, i don't know do you understand what i said previous.

The first, you say BIOS can cause this situation. But in 5.2.3 on page 72 of the document # 547869 [Rev 1.5]. Before CPU fetching BIOS code, the PLTRST# should de-asserted.

Second, you last suggestion is verify if the LPC_clkout1 can operate at 19.2 MHz. I already answer you that the LPC_clkout1 is NC status in our board, there is no test point, i can't verify it.

Third, Do you pay a attention to my issue? Or do you understand what i said? The Intel support is such things like this? I ask the CCE(ccechina.intel.com) for help, they say they know nothing about this issue,and you must do as the PDG or CRB. Then i want to ask this community for help, OK, the result is terrible.

Thanks for all your help!

View solution in original post

CarlosAM_INTEL · ‎04-12-2021

Hello, @B-OatPQURE:

Thanks for your reply.

Could you please clarify the part number of the Intel product related to your update?

We are waiting for your answer.

Best regards,

@CarlosAM_INTEL.

B-OatPQURE · ‎04-13-2021

This applies to every SoC requiring ME/TXE firmware/software in flash partition. Baytrail was the last Atom architecture where the integrated firmware in the SoC released the reset for the BSP without a ME/TXE partition in the SPI flash.

As Intel says that the Braswell architecture requires ME/TXE, it's pretty safe to assume that the reset to the BSP will not be released without a proper BIOS and ME/TXE software in flash partitions.

I will have the opportunity to validate if my assumption is right soon, so I can make an update of the fact if that would be helpful for anyone.

CarlosAM_INTEL · ‎01-12-2017

Hello, Sco35:

Thank you for contacting Intel Embedded Community.

In order to help you, we suggest address your request by filling out the https://www-ssl.intel.com/content/www/us/en/secure/forms/design-assistance.html Design Assistance form.

We hope that this information is useful to you.

Best regards,

Carlos_A .

JLian12 · ‎10-24-2017

Hi Kevin,

I also meet this issue and I fixed this issue. It seems some power not supply to SOC.

After check all power really to SOC, the PLTRST# will pull up after COREPWROK.

You can check PCIE power (V1P05) first. Other cause PLTRST# can not pull up I met

is worng power sequence and BATLOW# always low. You can check these items.

F.Y.I.

JackLiang