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Hello all,
Has anyone had any success implementing the SPI controller in the PCU in an Atom E3800 series processor?
I am trying to use the PCU SPI to configure a flash device, but I am having no luck in accessing the controller. Any reads to the SPI base address B/D/F located at 0/31/0 + 0x54 offset results in a read value of 0xFED01002.
Does anyone have any information on this? I did some research on this resulting value and upon looking at some Chipsec dumps, it seems to mean something, but I cannot figure out what exactly.
In any case, I just can't access my flash device using the SPI controller. When I attempt to read the hardware sequencing status register (HSFSTS) at offset 0x4, it returns a 0x2, indicating the FCERR bit is set. The datasheet says this is set by hardware if there's a "protection policy" configured, but it never clarifies what these "protection policies" are.
I am using an RTOS (not Linux or Windows), so I can't run any utilities.
There's very little information about this part online so I'm hoping to get answers here. Thank you for any tips or suggestions.
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Hello @AtomHelp,
Thank you for contacting Intel Embedded Community.
We are not supporting Bay Trail family anymore.
https://www.intel.com/content/www/us/en/support/articles/000022396/processors.html
I'm not sure if what you are trying to do can be done according to this.
https://www.mail-archive.com/coreboot@coreboot.org/msg49652.html
Also, I'm sharing the link for Bay Trail documents. You may check them to see what is available.
https://www.intel.com/content/www/us/en/products/platforms/details/bay-trail/docs.html
Best regards,
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Hello Diego,
Thanks for the links.
According to the Coreboot post, it seems the PCU SPI controller cannot be seen in the OS. I will continue to do research on this topic and post here if I find anything.
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Hello @AtomHelp,
Yes, that's why I'm not sure if it can be done but if you find anything else, it may be very interesting to know.
Best regards,
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