I am developing COMExpress using Atom E3950.
Therefore, I would like to confirm the following about PCIe regarding this SoC.
1.Provide the IBIS_AMI for the PCIe lane
2.Provide PCIE reference clock transmit characteristics
3.When fanning out the PCIe reference clock from the SoC, does the clock buffer need zero delay characteristics? And need a PLL?
I am sorry if my English is not good in my first post.
Thank you for contacting Intel Embedded Community.
You can find the Apollo Lake I I/O Buffer Information Specification IBIS Models document # 562905, Apollo Lake Platform SoC IO Buffer Information Specification IBIS Models document # 559409, Apollo Lake F1 IBIS files document # 596034, and Apollo Lake LPDDR4 - IBIS Model document # 572670 are the available IBIS model information.
You can find the answer to your second question in the specification of the standard stated in Table 3-15, on page 78 of the Intel Pentium and Celeron Processor N- and J- Series External Design Specification (EDS) Volume 1 of 4 document # 557555.
You can find the answer to your last question with the help of your Intel BIOS vendor in sections 3.3.1 and 3.3.18, on pages 25 and 34 of the Intel Pentium and Celeron Processor N- and J- Series Formerly Apollo Lake Intel Architecture Firmware Specification Volume 2 of 2 BIOS Specification document # 559811.
You can find these documents when you are logged into your Resource & Design Center (RDC) privileged account on the following websites:
The RDC Account Support form is the channel to process your account update request or report any inconveniences with the provided websites. It can be found at:
You can find the PCIe standard developer website as a reference on the following website:
Thank you for answers.
The RDC account took a time to acquire and the response was delayed.
I will check the contents from the documents that have been developed.
There is only one thing that I can't access the following site that I contacted.
I could access other places, but could you check them?