x5-E3930 Fast SPI

[MPippo]

On the data-sheet, at page #18, it’s mentioned that the Fast SPI is for TPM and Flash:

https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-processor-e3900-a3900-series-datasheet-addendum.pdf

Looking on the N and J Series, at page #85, it says that the Fast SPI has a clock of 14, 25, 40 and 50MHz.:

https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-j-series-datasheet-vol-1.pdf

Can you kindly confirm that the Fast SPI it’s only suggested by Intel to be used for TPM and BIOS due to the read speed compared to the SPI on the Low-Power Subsystem that can goes only up to 25Mb/s?

We would like to use the Fast SPI on the Q7 module to drive a FPGA on the carrier board and program it through the Fast SPI. Would it be possible or are there any issue?

[n_scott_pearson]

My understanding is that the SPI bus can be used to talk to up to 7 devices. In their example implementation, they have shown a TPM and a (single) flash component. I have seen implementations where two flash components are being used, so know that additional devices may be connected. Now, this is a high-level view; I have never been involved in the initialization of, or communication via, the SPI bus, so can't answer regarding any gotchas.

Hope this helps,

...S

[Oscar_A_Intel1]

Hello MPippo,

Thank you for posting on the Intel Community.

I can see you have questions related to the Intel Atom® x5-E3930 Processor. I will go ahead and transfer your thread to the Embedded community; so, they can further assist you.

Regards,

Oscar A. 

Intel Customer Support Technician

Under Contract to Intel Corporation

[CarlosAM_INTEL]

Hello, @MPippo​:

Thank you for contacting Intel Embedded Community.

The Apollo Lake – I devices (such the Intel Atom® x5-E3930 Processor) have the same Fast SPI features than the N- and J- Series Processors. You can confirm this information in Table 1, on page 11 of the Intel Atom® E3900 and Intel Atom®A3900 Processor Series External Design Specification (EDS) Addendum document # 336256 mentioned on the first communication of this thread.

Due to this fact, the Fast SPI communication is done through the SPI bus with a Master – Slave protocol. You can confirm this information in section 3.13, on page 79 of the Intel® Pentium® and Celeron® Processor N- and J- Series Datasheet – Volume 1 of 3 document # 334817 mentioned on your previous communication as well.

In order to answer your last communication, please review the information stated in section 28.3, on page 316 of the Intel(R) Pentium(R) and Celeron(R) Processor N- and J- Series [Formerly Apollo Lake] Platform Design Guide [PDG] document # 557775. It can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:

http://www.intel.com/cd/edesign/library/asmo-na/eng/557775.htm

The RDC Account Support form is the channel to process your account update request. It can be found at:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

Best regards,

@Mæcenas_INTEL​.