Inquiry Regarding Early 3.3 V Pull‑Up on FPGA I/O (Arria V GX) (5AGXMA5) on bank 7D

[Prashanth11]

I am contacting you regarding a power‑sequencing concern on an Arria V GX (5AGXMA5) device used in our design. Specifically, this question relates to Bank 7D, which is configured for 3.3 V single‑ended I/O.

Issue Description

In our system, certain I/O signals in Bank 7D are connected to an external slave device that uses 3.3 V pull‑ups on its side.
During system start‑up, the slave device powers up more quickly than the FPGA, resulting in the following condition:

• 3.3 V pull‑up from the slave device appears on the FPGA I/O pin BEFORE VCCIO for Bank 7D is powered,
• while FPGA core rails (VCCINT, VCCA) and other VCCIO rails are also still off.

Information Requested

To ensure reliable operation and avoid stressing the FPGA I/O structures, we would like clarification on:

1. Behavior of FPGA pins when an external 3.3 V signal is applied to an I/O in Bank 7D while VCCIO_7D is still off

   • Does this cause current to flow through internal ESD diodes or clamping structures?
   • Is there any risk of back‑powering, brown‑out latch‑up, or unintended partial powering of the bank?

2. Maximum allowable current into an I/O pin under this condition

   • What is the absolute maximum injection current permitted into an Arria V GX I/O pin when:
     • VCCIO for that bank is 0 V,
     • and the external signal is at 3.3 V from the slave device?
   • Are there any device‑level limitations or stress conditions defined for this scenario?

3. Recommended handling or sequencing

   • Does Intel recommend keeping all external I/O signals below a certain voltage until the FPGA VCCIO is valid?
   • Should we add series resistors, level isolation, or enforce a sequencing rule to avoid early I/O voltages?
   • Any specific guidelines for Arria V GX regarding I/O receiving voltages before VCCIO?

Background

This question arises because our system has a natural 1 ms sequencing offset, where the external device powers up quickly and asserts its pull‑ups before the FPGA supplies have stabilized.

We would appreciate Intel’s guidance so we can guarantee device safety and adjust our design if necessary.

Thank you very much for your support.

[Diego_INTEL]

Hello @Prashanth11,

Thank you for contacting Intel Embedded Community.

Please check the following regarding FPGA:

FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.

Best regards,

@Diego_INTEL