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Iris 5200 GPU and SDRAM memory controller TDP

NBodu1
Novice
2,199 Views

Hello

 

We have a problem with our application running on i7-4850 processor (47W TDP). We just cut DC power source wire and insert current measure tester into current path. Consumption for whole device is 35W without running our application and 72W with it. Even considering DC/DC converters chain efficiency as 85%, we get 37*0.85=31.5W. It's too much.

 

What our application does. It processes real-time 4K video data debayering from SDRAM, sends results to eDP port then. Other application (gstreamer) put data into SDRAM from PCIe for the processing. gstreamer consumes only 2W. GPU does all data processing, CPU is used as "Data pump" only.

So, the question is: which block could eat so much energy?

 

First candidate is DDR3L SDRAM, include SDRAM controller and its buffers. Memory massives are huge (~16M per one video frame), and, if data in SDRAM were not properly aligned to read, we have read of whole cache line by reading each required 2 bytes. 16 times or more overhead. Yes, I know that we need to add # pragma block_loop in code, to explore "space locality" memory property in cache, reading 16 data points per memory access, but we don't have code sources at the moment and have to speculate only. I also understand that proper way is to read data from PCIe to EDRAM buffer directly, without using SDRAM at all - it is not possible at the moment.

 

Second candidate is L3 cache. If data in memory were mapped so bad during write that we can't explore "time locality" data property during read, we have giant cache processing without any useful results, while cache is one of most power consumers in processor.

Third candidate is GPU. I can't make any conclusions because I don't have any data about GPU power consumption. I heard estimation as "10-15% of TDP", but I'm afraid it were speculations, too.

 

Can anyone suggest me document # which describes power comsumption of Haswell-M building blocks to make some conclusions about power optimization way?

 

With best regards,

Nikolay

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CarlosAM_INTEL
Moderator
948 Views

Hello DarkTiger,

Thank you for contacting the Intel Embedded Community.

The information that may help you is stated in the https://www-ssl.intel.com/content/www/us/en/secure/intelligent-systems/privileged/mobile-4th-gen-cor... Mobile 4th Gen. Intel(R) Core(TM) Platform Thermal Mechanical Design Guide.

Please let us know if this information is useful to you.

Best Regards,

Carlos A.

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5 Replies
CarlosAM_INTEL
Moderator
949 Views

Hello DarkTiger,

Thank you for contacting the Intel Embedded Community.

The information that may help you is stated in the https://www-ssl.intel.com/content/www/us/en/secure/intelligent-systems/privileged/mobile-4th-gen-cor... Mobile 4th Gen. Intel(R) Core(TM) Platform Thermal Mechanical Design Guide.

Please let us know if this information is useful to you.

Best Regards,

Carlos A.

NBodu1
Novice
948 Views

Hello Carlos,

 

Thank you very much for this link.

 

This document considers processor package as a whole piece that is required to cool. However, we use off-the shelf cooling plate from Kontron.

 

Despite of this, I found some very interesting points in this guide. I saw at pictures of temperature distribution inside processor package (p.37) that GPU (its place inside packages described on p.11) is not a hot point, which means that it isn't most power consuming block. This way, the problem source is inside CPU core or L3 cache. (I suppose that "OPCM" term in this document relates to EDRAM (128 M), not to 6M processor CPU cache)

 

Really, last page was extremely useful, too, because it contains documents # I need. Could you suggest links on documents:

490080 Configurable TDP and Low Power Mode Haswell Implementation Guide

509222 Shark Bay Thermal Management Design Guide (I suppose it is latest version of current document)

490079 Intel® Turbo Boost Technology 2.0 Haswell Implementation Guide

496300 Shark Bay Platform – Dynamic Power Performance Management (DPPM)

487822 Shark Bay Mobile Platform Power Delivery Design Guide

 

With best regards,

Nikolay Bodunov

CarlosAM_INTEL
Moderator
948 Views

Hello DarkTiger,

Thanks for your reply.

You can download the requested documents at the following web sites:

http://www.intel.com/content/www/us/en/secure/embedded/nda/products/haswell/tdp-lpm-4th-5th-gen-core... 490080 Configurable TDP and Low Power Mode Haswell Implementation Guide

http://www.intel.com/content/www/us/en/secure/embedded/nda/products/shark-bay/4th-gen-core-thermal-m... 509222 Shark Bay Thermal Management Design Guide

http://www.intel.com/content/www/us/en/secure/embedded/nda/products/haswell/4th-gen-core-processor-t... 490079 Intel(R) Turbo Boost Technology 2.0 Haswell Implementation Guide

http://www.intel.com/content/www/us/en/secure/embedded/nda/products/shark-bay/4th-gen-core-dynamic-p... 496300 Shark Bay Platform – Dynamic Power Performance Management (DPPM)

http://www.intel.com/content/www/us/en/secure/embedded/nda/products/haswell/power-delivery-4th-5th-g... 487822 Shark Bay Mobile Platform Power Delivery Design Guide

Please let us know if this information is useful to you.

Best Regards,

 

Carlos A.
NBodu1
Novice
948 Views

Thank you, Carlos! Exactly what I need.

CarlosAM_INTEL
Moderator
948 Views

Hello DarkTiger,

We are glad to hear that the provided information was useful to you.

Please do not hesitate to contact us again if you will have more questions related to Intel Embedded devices.

Best Regards,

Carlos A.

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