PCIe Gen5 on Alder Lakes

SteveMiller · ‎10-04-2023

We have a custom motherboard designed by a third party that using the 13th Gen i5-13500E . The ID number is 0xB06F2. The X16 PCIe port is routed off the motherboard to a Broadcom switch on our hardware. The X16 PCIe port runs well with good lane margin in both directions at Gen4. However, when we switch to Gen5, it has difficulty in linking and when linked throws lots of AER errors. The lane margin from the CPU as the transmitter to the Broadcom switch as the receiver is marginal. However, the lane margin from the Broadcom switch as the transmitter to the CPU as the receiver is extremely poor to almost zero.

Is there any known issues with this for this processor?

Is there any special settings or workarounds for this?

Any ideas why the margin is so bad in only one direction?

Thanks.

IsaacQ_Intel · ‎10-05-2023

Hello @SteveMiller

Thank you for posting on the Intel️® communities.

We will move your question to the correct sub-forum, the team in charge will get back to you soon.

Best regards,

Isaac Q.

Intel Customer Support Technician

SteveMiller · ‎10-10-2023

Is there any timeline for moving this to the sub-forum and responding to me?

Thank you.

Diego_INTEL · ‎10-13-2023

Hello @SteveMiller,

Thank you for contacting Intel Embedded Community.

My apologies for the delay in the response.

I have been checking internally and found in reports an issue in channel loss that occurs with PCIe Gen5 meanwhile in Gen4 there is no issue, but for another model of Raptor Lake. It appears as fixed but being a third-party device, you must contact the company that made the design of the board about your issue.

Best regards,

@Diego_INTEL

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