[Rangeley] How to disable Rangeley internal UART?

[JLee169]

Hi All,

My platform is Rangeley + winbond w83627DHG, and BIOS is cioreboot mohonpeak +Intel FSP,

according platform layout I need to disabe Rangeley uart and enable w83627DHG COMA, but follow below

implement procedure, the data can't output 3f8h, look like the 3f8h space have conflict, but on AMI

BIOS is working fine,have any one know it? Am I loss some step? thanks.

1. Disable INTEL internal UART 0,1F,0 +80 ----> 00

2. Enable 83627 COM A

1. setup muti function pin

2. initial COM A to 3f8h irq4.

James

[Adolfo_S_Intel]

Hello James_Lee

We are investigating your issue, and will contact you when we have useful information for you

Best regards,

Adolfo.

[Adolfo_S_Intel · Accepted solution]

Hello James_Lee

I was checking the datasheet for the Rangeley: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-c2000-microserver-datasheet.pdf http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-c2000-microserver-datasheet.pdf

I see that you are writing to B:0,D:0x1F (31), F:0+80 But the UART_CONT is the Bus:0, Device: 30 (0x1E), Function:0, Offset 80. (See the datasheet, Vol.2, page 464)

Hope this information is useful to you.

Best Regards,

Adolfo.

[JLee169]

Hi Adolfo,

The datasheet page 463/509 device is 31, on page 464 is 30.

and checked ami code is device 31, from "RW" tool to scan

LPC(ISA) device is on 0,1f,0, 0,1E0,0 is empty...

However I have test to disable 0,1e,0 also can NOT to fix this issue.

[Adolfo_S_Intel]

Hello James

Enable 83627 COM A

1. setup muti function pin

2. initial COM A to 3f8h irq4.

I'm not sure if I understand clearly the point number 2.

Could you clarify the following questions?

1) When you talk about 3F8h are you talking about the Fixed I/O Map that is on table 10-4 of the datasheet?

2) Are you enabling IRQ4 on the Windbond?

3)Are you using the APIC or the internal PIC?

4)Did you enabled the SERIRQ interruptions in the Rangeley?

Best Regards,

Adolfo

[JLee169]

Hi Adolfo,

Happy new year, thanks you respond so quickly, please see below my answer,thanks.

1) When you talk about 3F8h are you talking about the Fixed I/O Map that is on table 10-4 of the datasheet?

yes. AMI also use 3F8/IRQ 4 on w83627.

2) Are you enabling IRQ4 on the Windbond?

yes, same AMI.

3)Are you using the APIC or the internal PIC?

yes, coreboot use APIC.

4)Did you enabled the SERIRQ interruptions in the Rangeley

yes, coreboot default enable SERIRQ, and continue mode.

[Adolfo_S_Intel]

Hello James_Lee

Sorry for the long delay

I'm consulting your issue with our Intel Division.

In the meantime could you please answer the following questions to gather more information about your issue:

Could you please tell me what registers are you configuring in the W83627DHG, and what values are you using?

What happens when you try to read from 3F8h?

Does AMI BIOS also use the APIC or the PIC8259?

Do you know if the W83627DHG is being positively decoded, or substractively decoded?

Do you have access to the content of the CPU registers? If yes could you please compare the content of the following registers: LPCC, IRQEN, SCNT, OIC,

IR31,PIRQA-PIRQH, when using AMI BIOS and when using Coreboot?

Best regards,

Adolfo

[JLee169]

Hi Adolfo,

please see below my answer, thanks.

Could you please tell me what registers are you configuring in the W83627DHG, and what values are you using?

James: globel registers 24:clock select. 29: mutipin select to select UARTA pin, other 24~2E same AMI .

UARTA 30:enable 60/61: address 3F8 70: IRQ 4

these parts is same AMI.

What happens when you try to read from 3F8h?

James: always is value 08h.

Does AMI BIOS also use the APIC or the PIC8259?

James: AMI is PIC8259.

Do you know if the W83627DHG is being positively decoded, or substractively decoded?

James: no, I dont know , datasheet no write this.

Do you have access to the content of the CPU registers? If yes could you please compare the content of the following registers: LPCC, IRQEN, SCNT, OIC,

IR31,PIRQA-PIRQH, when using AMI BIOS and when using Coreboot?

James: I have follow AMI to fine tune these resisters, also can not to fix issue.

So far on BIOS post time no console message out, and on DOS mode also can NOT R/W 3F8h,

Best Regards

James

[Adolfo_S_Intel]

Hello James_Lee

Sorry for the delay.

So far the only difference I have noticed in your setup is that Coreboot is using the APIC, while AMI Bios is using the PIC controller.

Is it possible to you to try configuring the Coreboot to use the PIC, and test the results?

Best Regards,

Adolfo.

[JLee169]

Hi Adolfo,

Issue already fixed, I borrow a scope, and measure w83627pin waveform,

I find the 48M clock is no input.

So Rangeley disable UART code is right.

Superio UART implement code is correct.

Clock generator coding is wrong.

so UART is work fine now, thank your help.

Best Regards

James

[Adolfo_S_Intel]

Hello James_Lee

I'm glad that your issue has been solved.

And thanks for taking the time to come back to us and explain how you solved your problem, feedback from users of the community is really important and can help people with similar issues in the future.

Best regards,

Adolfo.