We have designed a custom board with D1559 processor, while doing the board bring up we noticed that ME region loads and releases the PLTRST , and serial console starts , but it stops printing and enters S3 state and asserts the PLTreset. After few seconds (4sec) it comes out of the sleep state and releases the reset. we would like to know the cause of the issue and how to solve it.
we also tried printing the messages continuously in the bios it self before it loads the memory it self , still we see the same issue.
Thank you for contacting Intel Embedded Community.
Could you please let us know how many units of the project related to this circumstance have been manufactured? How many are affected? Could you please give the failure rate? Also, could you please list the sources that you have used to design it and if it has been verified by Intel? Could you please let us the procedure that you have followed to determine this issue?
Could you please give pictures of the top side markings of the processors?
We are waiting for your reply to these questions.
Total of 11boards have been manufactured,
All 11 number have the same Affect,
Failure rate is 100%,
we have used the CRB as reference
The design is not reviewed by intel,
Procedure for determining,
- we flashed the bios image in the Custom board
- Wired the UART 0 pins to uart to usb converter
- when powered on we saw the debug messages in the terminal, but data stops half way.
Thanks for your reply.
Based on your previous message, could you please clarify if the BIOS associated to this condition has been implemented by a third-party developer or it is Customer Reference Board (CRB) BIOS?
Could you please confirm that the affected implementations have the latest Microcode Update (MCU)? In case that you need to obtain it, please follow the procedure stated in the GitHub(R) MCU Repository Training document # 607131. It can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:
The RDC Account Support form is the channel to process your account update request or any inconvenience related to the provided website. It can be found at:
We are waiting for your clarification.
We have updated the Microcode to latest available in GITHUB
Old Microcode: M10506654_0F00000A.h
New Microcode: M10506654_0F000017.h
We are using coreboot BIOS with Intel FSP1.0 for Broadwell-DE. FSP Version: BDXDE_FSP_MR_002_RC5_20161115
we noticed that previously we had reset happening 2 times with old micro code, but with new micro code we saw that it was resetting once. ie, PLTRST signal is asserted(for 4 seconds), after some time of BIOS boot. during this time SOC also enters the sleep state for 4 sec.
Please suggest any other things to be done.