We received HSPICE simulation models (545924-bdw-de-ddr4-si-model-rev0p95.zip) from Intel. We couldn't able to find the timing parameters for Intel Xeon D1559 in simulation file. Can you able to provide timing parameter for that?
Is any add-on or additional tools required to perform SI simulation apart from HSPICE? Pls confirm.
Thanks in Advance.
Thank you for contacting Intel Embedded Community.
The information that may help you can be found in the Intel Xeon D-1500 Product Family DDR4 Signal Integrity Model Users Guide [MUG] document # 545924, specifically in sections 5.3.5 and 5.3.6, on page 36 of the PDF file include in the cited document. It can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:
The RDC Account Support form is the channel to process your account update request and any inconvenience related to the cited sites. It can be found at:
Thanks for your prompt response.
We plan to use some other internal EDA tool (like HyperLynx, Sigrity). Is any add-on or additional tools required to perform SI simulation apart from HSPICE, in DDR4 simulation? Pls confirm.
Thanks in Advance,
Thanks for your update.
For this propose please refer to the information stated in section 4.6, on pages 26 and 27 of the PDF document mentioned in our previous communication to help you.
Please review the information stated in sections 4.4.92 through 4.4.98, 4.4.125, and 9.1.36; on pages 387 through 390, 405, 406, and 1616 of the Intel Xeon Processor D-1500 Product Family External Design Specification (EDS), Volume Two: Core and Uncore Registers document # 544041.
Also, please check the information stated in section 2.3, on pages 8 through 11 of the Intel Xeon Processor D-1500 Product Family Datasheet, Volume 3: Electrical document # 332052.
These documents are accessible when you are logged into your Resource & Design Center (RDC) privileged account at the following websites: