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Maximum eMMC size supported by Intel Xeon D-1746.

Raj_Kr
Novice
2,109 Views

Hi,

 

I am using Intel Xeon- D1747 Processor in my design. The processor supports eMMC 5.1 specification. 

But the datasheet doesn't say about the Maximum Size/density of eMMC supported.

Please help me out with this. 

 

Thank You

Raj Kumar

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BrusC_Intel
Employee
2,084 Views

Hello, Raj_Kr.


Thank you for posting on the Intel Community Support forums.


I will move your thread to the dedicated community for this type of product so it can be resolved as soon as possible.


Best regards,


Bruce C.

Intel Customer Support Technician


View solution in original post

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BrusC_Intel
Employee
2,085 Views

Hello, Raj_Kr.


Thank you for posting on the Intel Community Support forums.


I will move your thread to the dedicated community for this type of product so it can be resolved as soon as possible.


Best regards,


Bruce C.

Intel Customer Support Technician


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Diego_INTEL
Moderator
2,071 Views

Hello @Raj_Kr,

 

Thank you for contacting Intel Embedded Community.

 

Can you confirm me which processor are you using (the ones in the title and details are different) and the document number too please.

 

Best regards,

@Diego_INTEL 

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Raj_Kr
Novice
2,052 Views

Hello @Diego_INTEL 

 

Thank you for the reply. 

 

The processor details are as follows: - 

Intel® Xeon® D-1746TER 

(Ordering P/N: FH8068604436317)

 

Reference Number: 576513 (Idaville LCC)

Reference Number: 595910 (Volume1)

Reference Number: 595914 (Volume3)

 

And other documents as given in the attached screenshot-

 

Thank You 

Raj Kumar

 

 

 

 

 

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Diego_INTEL
Moderator
1,928 Views

Hello @Raj_Kr,

 

Thank you for the confirmation. I looked for some Product Component List documents but I have not find any under Idaville.

There is one for Elkhart Lake family, it does have the same eMMC specifications, at least to have a reference.

 

For the maximum density I have not find any limit, but Intel tested one eMMC of 64 GB, for higher densities you must verify it, but 64-128 GB should work.

The size of the device tested is 11.5 x 13 x 1.1 mm.

 

You may use this as a reference, also document #615156 at page 57 for more eMMC details.

 

I hope this helps, my apologies for not giving exact values.

 

Best regards,

@Diego_INTEL 

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Raj_Kr
Novice
1,878 Views

Hi @Diego_INTEL ,

 

Thanks for the information. 

In the JEDEC standard (JESD84-B51), The way of calculating maximum supported size of eMMC is explained as shown in  attached screenshot- 

But the problem is the required information (internal resistors values i.e. C_SIZE, C_SIZE_MULT, READ_BL_LEN, etc are not given in Xeon datasheets. 

 

And, I also found some article saying that eMMC size doesn't have any upper limit for controller. 

 

I think I don't have access to the document you suggested in last mail (document #615156 at page 57 for more eMMC details). 

 

Thank You 

Raj Kumar

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Diego_INTEL
Moderator
1,863 Views

Hello @Raj_Kr,

 

Thanks for sharing. Yes, you don't need this other document, you can work with what you have already.

 

You can use the document #576513 - PDG, in chapter 12 there is further information about resistor's values and an interface topology diagram for eMMC that may be helpful.

 

Best regards,

@Diego_INTEL 

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Raj_Kr
Novice
1,849 Views

Hi @Diego_INTEL

 

Thank you so much for the help!

In the same project (with Intel Xeon), I have one more doubt regarding eSPI/LPC Interface. 

As we know there are 2 no's of dedicated SPI interface for Boot Flash (BIOS Booting). 

And, one muxed eSPI/LPC interface to mainly interface with board management controller (BMC/EC). 

Now. I wanted to know that whether I can connect Boot Flash (BIOS booting) over eSPI/LPC interface also?

And, Can I connect a LPC to UART (RS232) converter on this (LPC) interface?

 

Thank You

Raj Kumar

 

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Diego_INTEL
Moderator
1,811 Views

Hello @Raj_Kr,

 

1)Yes, in page 642 of the same PDG, you should can according to this:

Boot BIOS Strap I Yes Selects the location of BIOS EPROM 0 = BOOT FROM SPI (DEFAULT), 1 = BOOT FROM ESPI/LPC.

 

Also, you may check the section "29.5.1.1 BIOS Direct Read in Descriptor Mode" in the document #595910 - EDS.

 

2) As for UART over LPC BUS, it may be possible. You may check section "Table 3-2. Host Fixed I/O Address Space " of the document #595910 - EDS.

If you will not use UART, you may hide it and assign the registers to the LPC interface.

Recommended section "28.4.1 UART Hiding and Locking" of the same EDS.

 

Best regards,

@Diego_INTEL 

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Raj_Kr
Novice
1,694 Views

Hello @Diego_INTEL 

 

You are requested to please share the footprint (.dra or .brd) file of Intel Xeon D-1746TER (FH8068604436317). 

Our Tool: Allegro PCB Editor 16.2 version. 

 

Thank You 

Raj Kumar

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Diego_INTEL
Moderator
1,681 Views

Hello @Raj_Kr,

 

You may check the document #616683 - Idaville LCC Platform: Brighton City Board Layout, in RDC.

 

Best regards,

@Diego_INTEL 

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Raj_Kr
Novice
1,475 Views

Hi,

 

I am planning to use CPLD (Intel Max 10 FPGA) in our design with Intel Xeon.

For the reference I need the corresponding design documents, CAD symbols, footprint, all type of datasheet, etc of Intel Max 10.

You are requested to provide me the access for the same.

 

Thank You 

Raj Kumar

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Diego_INTEL
Moderator
1,450 Views

Hello @Raj_Kr,

 

You may check in RDC all the documentation related to the Intel® MAX® 10 FPGA:

https://www.intel.com/content/www/us/en/products/details/fpga/max/10/docs.html

 

As this Forum is for Embedded products, it may be best that you use the FPGA support if you need any help with the device.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/overview.html

 

Best regards,

@Diego_INTEL 

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