NOR FLASH interface to Xeon D 1559

[Jinto]

Is there a provision to interface Larger (256 MB)NOR FLASH to XeonD 1548/1559?We do not want to use NAND FLASH supported on SATA. We want to explore these possibilities. 

1. Can a larger NOR FLASH (256MB) be connected to SPI0 and SPI1 and increase address space?

2. Can LPC bus be used for a NOR FLASH interface? Is there any reference design available?

[CarlosAM_INTEL]

Hello, @Jinto:

Thank you for contacting Intel Embedded Community.

The information that may help you can be found on pages 176, 177, and 178, in sections 3.23.4 of the Intel(R) Xeon(R) Processor D-1500 Product Family External Design Specification (EDS) Volume 5: Integrated PCH document # 544044; and pages 209, 210, 277, and 278, in sections 9.3.1, 13.4, and 13.5 of the Grangeville with Intel(R) Xeon(R) Processor D-1500 Product Family Platform Design Guide (PDG) document # 543448. They can be found when you are logged into your Resource & Design Center (RDC) privileged account on the following websites:

http://www.intel.com/cd/edesign/library/asmo-na/eng/544044.htm

http://www.intel.com/cd/edesign/library/asmo-na/eng/543448.htm

The RDC Account Support form is the channel to process your account update request or report any inconveniences with the provided site. It can be found at:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

[Jinto]

Looks like we can expand LPC bus up to 256MB per device with additional glue logic in FPGA. Is it possible to modify SPI FLASH range to 256MB? If possible, how to achieve this?

[CarlosAM_INTEL]

Hello, @Jinto:

Thank you for contacting Intel Embedded Community.

The information that may clarify this situation can be found in sections  2.6.1, 2.7, 3.1.1, 4, 4.1.2.1, 4.1.7.2, 4.1.7.4, 4.4.2, 6.4, 6.6, 7.2.1, 8.2, 8.3, 9, and A.2 of the Intel(R) 9 Series Chipset Family SPI Programming Guide document # 539903, and in sections 2.6.1, 2.7, 3.1.1, 4, 4.1.2.1, 4.1.7.4, 4.4.2, 6.4, 6.6, 7.2.1, 8.2, 8.3, 9, 12.2, and A.2 of the Intel(R) 8 Series Chipset Family SPI Programming Guide document # 560858.They can be found when you are logged into your Resource & Design Center (RDC) privileged account on the following websites:

http://www.intel.com/cd/edesign/library/asmo-na/eng/539903.htm

http://www.intel.com/cd/edesign/library/asmo-na/eng/560858.htm

The RDC Account Support form is the channel to process your account update request or report any inconveniences with the provided site. It can be found at:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.