Question about Xeon D-2100 series circuit design

[ZShin]

Hi all.

I have a question about Xeon CPU circuit design.

In order to design the mother board I'm referring the CRB circuits, EDS and PDG documentations. (doc #573770-yubacity-10l-collateral-final-rev1-1, 568202_D-2100_EDS_Rev2_3 ,568130_Bakerville_PDG_Rev2_8)

But, some of the guides show different scheme on CRB vs PDG or EDS.

For example, on the PDG p.360 describes "unused SATAGP/sSATAGP pins must be terminated to either Vcc3_3rail or GND using 8.2Kohm to 10Kohm resistor on the motherboard. Either pull-up or pull-down is acceptable" however, on the CRB p.32, unused SATAGP 5, 4, 3 pins are floating.

So, this makes me confusing.

Please let me know, which guideline should I follow? or which guideline has higher priority?

Thanks in advance

Joe

[Leonardo_C_Intel]

Hello ZShin

Thank you for posting in the Intel Community.

we have a forum for your specific issues and I am moving your question to Embedded Developers so it can get answered more quickly.

Regards,

Leonardo C.

Intel Customer Support Technician

[CarlosAM_INTEL · Accepted solution]

Hello, @ZShin:

Thank you for contacting Intel Embedded Community.

You should use the latest version of the documentation to implement properly your design because it includes corrections and workarounds that are not included in previous versions.  

Best regards,

@CarlosAM_INTEL.

[ZShin]

Hi, @CarlosAM_INTEL 

Thank you for the reply.

Then, PDG is more reliable in this situation. Since, PDG updated this year but CRB's last update date is 2017.

Thank you again.

Best.

Joe.