I have a question about Xeon CPU circuit design.
In order to design the mother board I'm referring the CRB circuits, EDS and PDG documentations. (doc #573770-yubacity-10l-collateral-final-rev1-1, 568202_D-2100_EDS_Rev2_3 ,568130_Bakerville_PDG_Rev2_8)
But, some of the guides show different scheme on CRB vs PDG or EDS.
For example, on the PDG p.360 describes "unused SATAGP/sSATAGP pins must be terminated to either Vcc3_3rail or GND using 8.2Kohm to 10Kohm resistor on the motherboard. Either pull-up or pull-down is acceptable" however, on the CRB p.32, unused SATAGP 5, 4, 3 pins are floating.
So, this makes me confusing.
Please let me know, which guideline should I follow? or which guideline has higher priority?
Thanks in advance
Thank you for posting in the Intel Community.
we have a forum for your specific issues and I am moving your question to Embedded Developers so it can get answered more quickly.
Intel Customer Support Technician