We are redesigning the board with on board X8 DDR4 devices, while cross checking the reference design we saw that the TDQS line of the DDR4 chips are connected to the DQS 9-17 of the xeon.

[KMANO3]

Are those TDQS connection mandatory? Also we are not using the registers for the address and command lines, is this okay?

Also we would like to know whether the SOC DDR clock can drive 9 chips as we are using single rank configuration.

[CarlosAM_INTEL]

Hello, @KMANO3​:

Thank you for contacting Intel Embedded Community.

In order to help you, we want to address the following question:

Could you please confirm if this thread is related to the followings?

https://forums.intel.com/s/question/0D50P00004VGKGpSAP/ddr4-controller-timing-parameters-in-xeon-d1559

https://forums.intel.com/s/question/0D50P00004cB9UvSAK/memory-detection-issue

https://forums.intel.com/s/question/0D50P00004Zl5B3SAJ/could-you-please-confirm-the-processor-xeon-d1559-can-support-8gb-technology-with-x16-adddressing-for-ddr4-memory

https://forums.intel.com/s/question/0D50P00004ZRf2CSAT/ddr4-sdram-memory-test-failure

https://forums.intel.com/s/question/0D50P00004WxuaQSAR/ddr4-analysis-using-mbere-tool

https://forums.intel.com/s/question/0D50P00004VGKGpSAP/ddr4-controller-timing-parameters-in-xeon-d1559

https://forums.intel.com/s/question/0D50P00004cZ7TfSAK/performed-ddr4-timing-analysis-broadwell-de-xeon-processor-d1559-ddr4-timing-parameters

Could you please confirm that you have received our communication via email of the past Thursday February 13th, 2020?

We are waiting for your confirmation.

Best regards, 

@Mæcenas_INTEL​.