I am using the X540-BT2 Ethernet controller in my design and I have a question regarding the SDP (software defined pins) pins.
The X540 reference schematic does not tie these pins high or low.
The X540 datasheet pin interface does not state that these pins have internal pull-ups or pull-downs. There is a Note 1 that states these pins should have external Pup/Pdn's.
In section 4.4.3 of the datasheet there is a statement that SDP0_1 and SDP1_1 have weak internal pull-down resistors.
The I350 schematic checklist states that the if the SDP pins are not used they can be left disconnected.
Do the SDP pins need to be connected to external pull-ups or pull-downs?
The SDP Control Register (Datasheet 18.104.22.168) in the NVM is configured as 0x0000 for LAN0 and 0x0400 for LAN1. Generic software controlled I/O. All SDP pins inputs except SDP1_2.
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I am having an issue with the X540 loosing PCIe link at slightly elevated die temps. I have this issue on multiple prototype boards.
The SPD pins are not externally terminated on this design. I am looking for design issues which could result in device noise - i.e. floating pins.
Thanks for your clarification.
Based on your previous replies, could you please tell us if your design has been reviewed by Intel?
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No the design has not been reviewed.
We use Altium which is not supported by Intel's automated review process.
Like I previously stated, the reference design for the X540 does not specifically state what to do with these pins.
The datasheet contradicts itself in various sections.
I do not use these pins. These pins are floating in my current design. What does Intel recommend?
We apologize for the delay to give you an update.
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