Xeon D-1539 integrated 10Gb phy power

[THabe2]

We have a Xeon 1539 10Gb KR connected via backplane to a Kintex Ultrascale (KU115) FPGA and are having data quality issues when sending from the Xeon to the FPGA. There are a lot of bit errors when transmitting known patters via UDP.

FEC is off; auto-neg and link training are on although there is some question as to whether the FPGA performs any analysis of the training data and just indicates the link is OK.

We have eye diagrams from the FPGA receive side that indicate a poor quality connection.

Are there any registers where we can tweak the power level (or other parameters) on the Xeon transmit side? I ask here because Xeon D1500 data sheet seems to be missing the integrated PHY registers(?). (Section 3.8.1 links to appendix B and appendix B(B.5) links to section 3.8.1)

[THabe2]

Think what I am looking for is documentation for the KR related registers. Don't seem to be in the D-1500 datasheet.

These are in the ixgbe driver (downloaded from intel) in ixgbe_type.h. Where can I find documentation for these?

# define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)

# define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)

# define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)

# define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)

# define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)

# define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)

# define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)

# define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)

# define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)

# define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)

# define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)

# define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)

# define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)

# define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)

# define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)

# define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)

# define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)

[CarlosAM_INTEL]

Hello, haberlan:

Thank you for contacting Intel Embedded Community.

In order to be on the same page, could you please clarify if the affected design has been developed by you or a third-party company? If it is a third-party design, please give us all the information related to it.

In case that it is your design, could you please confirm if the schematics and layout have been reviewed by Intel?

Waiting for the information that should answer these questions.

Best regards,

Carlos_A.

[THabe2]

Third party. https://www.xes-inc.com/products/sbcs/xpedite7676/ Xpedite7676

[CarlosAM_INTEL]

Hello, haberlan:

Thanks for your update.

Based on your previous communication, in order to give you the proper information related to this third-party implementation, you should address your consultations related to it as a reference at the channels listed at the following website:

https://www.xes-inc.com/support-services/support/ https://www.xes-inc.com/support-services/support/

We hope that this information will be useful to you.

Best regards,

Carlos_A.

[THabe2]

Apologies. The Xeon is an Intel part. The ixgbe driver I installed is from Intel website.

I am asking for documentation for the registers I mentioned in my posting, which were pulled from the ixgbe driver. I am unable to locate them in the D-1500 Vol 4 datasheet. There is some reference to the x550 family, but that part does not support KR.

By referring me to XES, are you saying that the D-1539 does not contain the KR auto negotiation and link training logic (and the registers)?

These are the macros I am referring to - where can I find the docs for them?

from ixgbe_type.h:

# define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)

# define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)

# define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)

# define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)

# define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)

# define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)

# define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)

# define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)

# define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)

# define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)

# define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)

# define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)

# define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)

# define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)

# define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)

# define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)

# define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)

[CarlosAM_INTEL]

Hello, haberlan:

Thank for your reply.

Actually, who can confirm if the proper driver to the cited third-party implementation is the cited should be its manufacturer.

It is important to let you know that Intel provided generic drivers to the third-party designs.

We hope that this clarification may help that you understand our last communication.

Best regards,

Carlos_A.