xeon D 1559

[Jinto]

Xeon D spec says maximum 32 lanes of PCIe is possible. Does it mean any lanes are multiplexed with SATA or any other interfaces? Do we need to compromise on any other interface to utilise all 32 lanes of PCIe?Where can we find relevant documentation? Please review feasibility of lane allocation in attached document

[CarlosAM_INTEL]

Hello, @Jinto:

Thank you for contacting Intel Embedded Community.

The information that may answer your questions stated in section 8.4, on pages 175, 176, and 177 of the Grangeville with Intel(R) Xeon(R) Processor D-1500 Product Family Platform Design Guide (PDG) document # 543448. It can be found when you are logged into your Resource & Design Center (RDC) privileged account on the following websites:

http://www.intel.com/cd/edesign/library/asmo-na/eng/543448.htm

The RDC Account Support form is the channel to process your account update request or report any inconveniences with the provided site. It can be found at:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.