I am trying to run the 40Gb Ethernet MAC/PHY IP provided by the OPAE. I am using the fpga-pac-a10 severs. Two problems I have here:
1. When testing the pre-built GBS from the example design with `hssi_loopback` utility, it complains that it cannot initialize the AFU.
$ hssi_loopback readmacs -B 0xAF Found e40 Error initializing accelerator
2. I also developed a simple AFU using `eth_e2e_e40` module provided in the example design. When running the example on Arria-10, the start signal of this module was set high, but the module never receives any non-zero PrMgmtCmd from the HSSI interface, and the `init_done` signal is always low (i.e. it is never initialized properly).
The PrMgmtCmd should have been configured correctly by writing the corresponding CSRs in the software using the `fpgaHssiSendPacket` API. What is the problem here?
Also, I am wondering if the fpga-bdx-opae platform can support the HSSI networking feature? It seems that this integrated FPGA-CPU platform should have support for HSSI: https://opae.github.io/latest/docs/fpga_tools/hssi_config/readme.html. But I go another another error when compiling the program (if I use the hssi interface in the AFU top-level module)
Error: ccip_std_afu needs port hssi:raw_pr that a10_gx_intg_xeon_bdx doesn't offer Error: "afu_platform_config --qsf --tgt platform --src=../../hw/rtl/eth_e2e_e40.json a10_gx_intg_xeon_bdx" failed
Thank you for posting in Intel Ethernet Communities.
Since your query is related to FPGA product, we suggest posting your query on the forum link below for further assistance.
Go to 'Featured Topic' > 'FPGA Developers' then, post question on the appropriate subforum topic.
Intel Community forums
Let us know if you have additional questions and clarifications.
Please be advised that we will proceed with request closure. Just feel free to post a new question if you may have any other inquiry in the future.
May you have an amazing day ahead!
Intel® Customer Support