We're planning a product with a 10 GBE Interface.
We want to use X550-AT2 as the controller.
The CPU in the system is a Q-Seven module.
The link between X550-AT2 and CPU is PCI-E Gen3。
In the datasheet of X550, the PCI-E width is described as x1, x4 or x8。But in our system, we can only use a x2 width。
I wonder whether the x2 width can be supported by X550-AT2? Or it can only be recognized as a x1 width?
Thank you for posting in Wired Ethernet Communities.
Based on page 2 of the X550 datasheet ( https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/ethernet-x550-datasheet.pdf), it mentioned "Removed x2 lane width".
Let me double check and update this thread as soon as possible.
Intel Customer Support
Agent under contract to Intel
Thanks a lot for your reply. I did miss the information in the Revision History.
In my understanding, now the question is, whether "Removed x2 lane width" means just fixing an error in the datasheet or adjusting the function of the chip?
I'm looking forward to your updating. Thanks again.