E810 Ethernet and PCIe Interface questions

[dkim_us]

I am using 16 E810s to for my design, N5426.

E810's are placed as a gateway between two IC devices on two separate PCB's.

Each E810 connects to a 100GE (two lanes of 50G-R: PAM4) and 8 lane PCIe v4. 

On the N5426 PCB, E810 interface thru 50G-R lanes to Marvell Falcon chip 98CX8580.

The 8 lanes PCIe v4  of E810's are connected to the connector for other PCB interface.

Please refer to the block diagram attached.

Questions:

1. E810 has 8 lanes of Ethernet, Lane0 thru Lane7: For two lanes for 50G-R, should I use lane 0 and lane 2?   if not which two lanes should I use?
2. I would like to use AC coupling capacitors on Ethernet lanes.   Does E810 Ethernet receiver input have internal bias (pull up to power)?
3. E810 has 16 lanes of PCIe, Lane0 thru Lane15: I am using using lane 0 thru lane 7 for 8 lane PCIe v4.  TX will have AC coupling capacitors.  The lane 8 thru lane15 are unconnected.  Let me know if you see any issue in what I described.

[B_Y]

Hello @dkim_us,

Thank you for posting in Intel Ethernet Communities. 

However, kindly note that you’ve reached a different forum, where the product you have mentioned is not supported. We are happy to inform you, that we have forwarded your request to the right team, who will check and revert to you at the earliest.

Thank you.

Best regards,

BY_Intel

Intel Customer Support 

[dkim_us]

Thank you for forwarding my question.

May I ask you to send me the direct link for the team responsible for E810 technical question, since I may need to communicate more questions for regarding E810?

[B_Y]

Hello @dkim_us,

We also noticed you have raised a request ticket with similar description from the Intel web portal. May I know if you would prefer to get support from community (which visible to public) or web portal.

Looking forward to hearing from you.

Best regards,

BY_Intel

Intel Customer Support 

[dkim_us]

Hi,

I would like to get support from the Intel support team.

I reposted the same questions to other portal (may be support community), because I was not too sure if I sent the question to the right portal.

Regards,

Dong

[B_Y]

Hello @dkim_us,

Based on the inquires, it is more related to PHY Lane Mapping which involved the architecture for the Intel® Ethernet Controller E810. Intel® Ethernet Controller E810 Datasheet Article ID# 613875 , page 109, URL: https://www.intel.com/content/www/us/en/content-details/613875/intel-ethernet-controller-e810-datasheet.html?wapkw=E810%20architectures&DocID=613875

May I know if this inquiry is related to Intel® Ethernet Controller or Network Adapter of E810? If it is an Intel Network Adapter E810, please share the model or a clear snapshot of front and back label of the NIC.

Thank you.

Best regards,

BY_Intel

Intel Customer Support 

[dkim_us]

My Inquiry is related to Ethernet controller E810-CAM1.

Thank you,

Dong

[B_Y]

Hello @dkim_us,

I hope this message finds you well. I am just sending a follow up if you have any questions from the previous post. If so, please let us know. Thank you.

Best regards,

BY_Intel

Intel® Customer Support

[B_Y]

Hello @dkim_us,

You may refer to page# 49, subject: 2.2 Pin Assignments and Descriptions.:

Datasheet URL: https://www.intel.com/content/www/us/en/content-details/613875/intel-ethernet-controller-e810-datasheet.html?wapkw=E810%20architectures&DocID=613875

May I know if information provided is sufficient?

Thank you.

Best regards,

BY_Intel

Intel Customer Support 

[dkim_us]

BY,

I did read the E810 datasheet Page49 and Page109 from the link you sent me.  I did read this and could not fine the clear answer.

I could not understand clearly which lanes I supposed to use for Ethernet side and PCIE side.

Please refer to the block diagram and the schematic excerpt in the file  I have attached on 10/12/23.

I have reattached the same file below.

Item number 1 has the overall block diagram for sixteen E810s connecting between Hirose connector and Falcon 98CX8580.

Item number 2 is the schematic for E810 PCIe v4. I am using The First 8 (lane0 thru lane7) of 16 lanes.

Item number 3 is the schematic for E810 Ethernet lanes, selecting Lane0 and Lane2, anticipating 50G bandwidth on each lane.  Aggregate 100G.

I apologize my question might have been unclear earlier.

Reiterating my E810 question:

1. Ethernet: Is it correct to select lane0 and lane2 to have 100G aggregate on a E810, anticipating 50G-R1 on each lane selected?

2. PCIe: To select 8 lane PCIe V4, is it correct to use Lane0 thru Lane7?  or should I select Lane8 thru Lan15?

I hope my question is more clearly conveyed this time.

Thank you,

Dong

[B_Y]

Hello @dkim_us,

I hope this message finds you well. I am just sending a follow up if you have any questions from the previous post. If so, please let us know.

Thank you.

Best regards,

BY_Intel

Intel Customer Support 

[Irwan_Intel]

Hello dkim_us,

Apologies for the delay in response. You inquiry is out of our support scope.

Please open an IPS case and our dedicated team will be in touch with you shortly.

We will go ahead and close this thread. Thank you.

https://www.intel.com/content/www/us/en/support/articles/000057045/ethernet-products.html

Regards,

Irwan_Intel