Community
cancel
Showing results for 
Search instead for 
Did you mean: 
AStoj1
New Contributor I
1,521 Views

Ethernet Compliance Test I210-AT 10Base-T/100Base-TX

Jump to solution

Hi

I want to run Ethernet Compliance Tests 10/100Mbps with I210-AT.

Are there any information available? I can not find anything in the datasheet.

E.g. create 100Mbps MLT-3 Random Test Pattern.

I can only find Test Mode Register Bits (15:13) in 1000Base-T Control Register (Page 0, Register 9) for Gigabit.

What is the purpose of 100 MB test select bits 3:2 of Copper Specific Control Register 3 - Page 0, Register 23 ?

What can I do with the PRBS Control - Page 26, Register 23 ?

Thanks for your help

Andrija

Tags (2)
0 Kudos
1 Solution
AStoj1
New Contributor I
226 Views

IEEE 10Mbps Tests: • Setup For All patterns – This needs to be done before sending packets with the listed payload below for each test. Ensures the link is forced up so packets will send and that no other 100/1G test modes are running. o Write MDIO Phy Register 0x10, Turn off bit 10 o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3 o Write MAC Register 0xE14, Turn off bit 5 o Write MDIO Phy Register 0x10, Turn on bit 10 o Write MDIO Phy Register 0x16, Set value to 0x6 o Write MDIO Phy Register 0x10, Set Value to 0x0 o Write MDIO Phy Register 0x16, Set Value to 0x0 o Write MDIO Phy Register 0x0, Set Value to 0x0 14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 5MHz) – Send 1500 Byte Packets containing AA pattern as the packet payload. 14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 10MHz) - Send 1500 Byte Packets containing FF pattern as the packet payload. 14.3.1.2.1 - Harmonic Content, All Ones Signal - Send 1500 Byte Packets containing FF pattern as the packet payload. 14.3.1.2.1 - Differential Output Voltage Template - Send 1500 Byte Packets containing Random data as the packet payload. 14.3.1.2.1 - TP_IDL Waveform Output – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0. 14.2.1.4 - RD Circuit Differential Input Impedance (Rx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0. 14.3.1.2.2 - TD Circuit differential Output Impedance (Tx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0. 14.3.1.2.5 - TD Circuit Common-Mode Output Voltage - Send 512 Byte Packets containing Random data as the packet payload. 14.3.1.2.3 - Transmitter Output Timing Jitter with Cable Model - Send 1500 Byte Packets containing Random data as the packet payload. 14.3.1.2.3 - Transmitter Output Timing Jitter without Cable Model - Send 1500 Byte Packets containing Random data as the packet payload. IEEE 100Mbps Tests: o Setup to be done before setting any patterns o Write MDIO Phy Register 0x10, Turn off bit 10 o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3 o Write MAC Register 0xE14, Turn off bit 5 o Write MDIO Phy Register 0x0, Set value to 0xA000 9.1.2.2 - UTP Differential Output Voltage – Should see 112ns wide pulses 9.1.4 - Signal Amplitude Symmetry 9.1.6 - Rise/Fall Times o Write MDIO Phy Register 0x1A, Turn on Bit 3 9.1.5 -Transmit Return Loss – Should see random idles data 9.1.9 - Transmit Jitter 9.2.2 - Receiver Return Loss o Write MDIO Phy Register 0x1A, Set Value to 0x0 9.1.8 - Duty Cycle Distortion (DCD) – Should see 16ns pulses o Write MDIO Phy Register 0x1A, Turn on bits 2 and 3 IEEE 1Gbps Tests Setup for all patterns o Write MDIO Phy Register 0x0, set value 0x9140 – This sets it to Gigabit and resets the adapter. 40.6.1.2.1 - Peak Differential Output Voltage (Test Mode 1) 40.6.1.2.2 - Maximum Output Droop (Test Mode 1) o Write MDIO Phy Register 0x9, set value 0x3B00 40.6.1.2.4 - Transmitter Distortion (Test Mode 4) 40.8.3.1 - MDI Return Loss (Test Mode 4) 40.8.3.3 - MDI Common-Mode Output Voltage (Test Mode 4) o Write MDIO Phy Register 0x9, Set value 0x9B00 40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 2) o Write MDIO Phy Register 0x9, Set value 0x5B00 40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 3) o Write MDIO Phy Register 0x9, Set value 0x7300

View solution in original post

2 Replies
idata
Community Manager
226 Views

Hi mailto:Andrija.stojkovic@toradex.com Andrija.stojkovic@toradex.com

 

 

Thank you for posting in Wired Communities. You may try registering at our Resource and Design center https://www.intel.com/content/www/us/en/my-intel/design-center-sign-in.html?redirect=/content/www/us... to gain access to the documents that required privilege access.You may check from there if the documents are available.

 

 

With regards to your inquiry about the register in the datasheet, you can try check with our embedded support at https://embedded.communities.intel.com/community/en

 

 

 

Regards,

 

Sharon T

 

AStoj1
New Contributor I
227 Views

IEEE 10Mbps Tests: • Setup For All patterns – This needs to be done before sending packets with the listed payload below for each test. Ensures the link is forced up so packets will send and that no other 100/1G test modes are running. o Write MDIO Phy Register 0x10, Turn off bit 10 o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3 o Write MAC Register 0xE14, Turn off bit 5 o Write MDIO Phy Register 0x10, Turn on bit 10 o Write MDIO Phy Register 0x16, Set value to 0x6 o Write MDIO Phy Register 0x10, Set Value to 0x0 o Write MDIO Phy Register 0x16, Set Value to 0x0 o Write MDIO Phy Register 0x0, Set Value to 0x0 14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 5MHz) – Send 1500 Byte Packets containing AA pattern as the packet payload. 14.3.1.2.1 - Peak Differential Output Voltage on TD Circuit (Amp 10MHz) - Send 1500 Byte Packets containing FF pattern as the packet payload. 14.3.1.2.1 - Harmonic Content, All Ones Signal - Send 1500 Byte Packets containing FF pattern as the packet payload. 14.3.1.2.1 - Differential Output Voltage Template - Send 1500 Byte Packets containing Random data as the packet payload. 14.3.1.2.1 - TP_IDL Waveform Output – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0. 14.2.1.4 - RD Circuit Differential Input Impedance (Rx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0. 14.3.1.2.2 - TD Circuit differential Output Impedance (Tx Return Loss) – Perform setup, do not send any packets. There should be an idle pulse always on after setting register 0x0 to 0x0. 14.3.1.2.5 - TD Circuit Common-Mode Output Voltage - Send 512 Byte Packets containing Random data as the packet payload. 14.3.1.2.3 - Transmitter Output Timing Jitter with Cable Model - Send 1500 Byte Packets containing Random data as the packet payload. 14.3.1.2.3 - Transmitter Output Timing Jitter without Cable Model - Send 1500 Byte Packets containing Random data as the packet payload. IEEE 100Mbps Tests: o Setup to be done before setting any patterns o Write MDIO Phy Register 0x10, Turn off bit 10 o Write MDIO Phy Register 0x1A, Turn off bits 2 and 3 o Write MAC Register 0xE14, Turn off bit 5 o Write MDIO Phy Register 0x0, Set value to 0xA000 9.1.2.2 - UTP Differential Output Voltage – Should see 112ns wide pulses 9.1.4 - Signal Amplitude Symmetry 9.1.6 - Rise/Fall Times o Write MDIO Phy Register 0x1A, Turn on Bit 3 9.1.5 -Transmit Return Loss – Should see random idles data 9.1.9 - Transmit Jitter 9.2.2 - Receiver Return Loss o Write MDIO Phy Register 0x1A, Set Value to 0x0 9.1.8 - Duty Cycle Distortion (DCD) – Should see 16ns pulses o Write MDIO Phy Register 0x1A, Turn on bits 2 and 3 IEEE 1Gbps Tests Setup for all patterns o Write MDIO Phy Register 0x0, set value 0x9140 – This sets it to Gigabit and resets the adapter. 40.6.1.2.1 - Peak Differential Output Voltage (Test Mode 1) 40.6.1.2.2 - Maximum Output Droop (Test Mode 1) o Write MDIO Phy Register 0x9, set value 0x3B00 40.6.1.2.4 - Transmitter Distortion (Test Mode 4) 40.8.3.1 - MDI Return Loss (Test Mode 4) 40.8.3.3 - MDI Common-Mode Output Voltage (Test Mode 4) o Write MDIO Phy Register 0x9, Set value 0x9B00 40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 2) o Write MDIO Phy Register 0x9, Set value 0x5B00 40.6.1.2.5 - Transmitter Timing Jitter (Test Mode 3) o Write MDIO Phy Register 0x9, Set value 0x7300

View solution in original post

Reply