Failing to upload code to NIOS2 processor

[Altera_Forum]

We have a DE4 university program board (Stratix IV SGX230) with triple-speed ethernet. We are attempting to run an example provided by Altera (ethernet accelerated design, written for our board) and even using Altera's precompiled .sof and .elf files. In Quartus 13.1, we receive the following error from the NIOS2 command shell: 

 Verifying 18000120 ( 0%) Verify failed between address 0x180000120 and 0x1800FFFF Leaving target processor paused  In Quartus 12.1, the version mentioned in the example readme file, it simply says "target processor not responding".   We tried compiling our own .sof file, but we ran into the same issue. It may be relevant that we are using a time-limited Open-Core. Any advice on how to handle such errors?   Thanks in advanced!

[Altera_Forum]

For the time limited cores, you need to download the SOF via JTAG and then keep that connection open/running (definition of "tethered") while doing anything else (including using the IDE to download the software). 

 Are you doing this? If not, then that very well could be your problem. With the time limited cores, you have to be tethered to any FPGA configuration "stream" containing them. It's not possible to program time limited versions into flash.  Best of luck!  slacker

[Altera_Forum]

That seems to have been the problem! We were quitting the time time limited function, because it seemed like this was necessary to upload code to the NIOS processor. But we just had to leave the NIOS2 terminal sitting on the screen saying "Info: Running Quartus II 32-bit Programmer... Please enter i for info and q to quit: " and then open another NIOS2 terminal to download the code to the NIOS2. 

 There are still lots of bugs, but we will have to discuss those on another forum. Thank you for your help!