Hello allI'm a master student I want to buy one FPGA Board+ADA card from Terasic I'm gonna generate a signal by DDS on the FPGA side and then Sample two signals. only one second sampling needs to 2x65Mx2Byte RAM space. then I need to some process on the sampled data such as Sliding FFT or Wavelet. then I need to transfer the Sampled data and the Results to my laptop over USB or Ethernet. i don't want to use linux at all.
all of my time is only 7 month. what should I do? which one is better and easier to control the RAM and USB or Ethernet? Nios or SOC? if there are any IP cores to control them, How much price is it usually? I couldn't find any price list on the Altera webpage! don't forget I'm a student not a billionaire! "Cyclone V Starter board" is suitable for me? or "DE-1 SOC"? I'm newbie to FPGA please help me in details bcoz I can not understand very professional discussions. Regards
The DE-1 SOC has an ARM processor. You will have to learn the interface from the ARM->FPGA.I am using the DE2-115. Feedback from my labmate (I am also an MS student) and his professor is that the DE-1 SOC is more challenging, since the ARM interface is a little more complicated than the Nios II direct interface. The Nios II and general IP cores are free to use. For that much RAM, you will need to use off-chip memory. There are separate tutorials at Altera University for SD-RAM. Be sure to adjust your (*.sdc) file to adjust for skew. If you are building a custom module, you will need to ensure your timing constraints in the Synopsis Design Contraint (.sdc) file with TimeQuest Analyze to ensure your logic paths meet timing requirements. Some helpful tutorials: Using the SDRAM (Altera University Program) - simple SDRAM controller with phase lock loop adjustments Using Triple Speed Ethernet (Altera University Program) - using PLLs, direct memory access controllers, on-chip RAM, triple speed ethernet module UDP Offload Example (AlteraWiki) For a lot of these tutorials, there is no Linux but you still use a processor to provide control. After FPGA logic synthesis, you will need to build Board Support Packet (BSP) in Eclipse EDS or command line. When you build it, you can specify the Altera Hardware Abstraction Layer (HAL) or Micrium MicroC/OS-II RTOS. MicroC/OS-II has a network stack you can use to send Ethernet frames. I believe you can also load linux onto it. If you don't want to use any Operating System and go full hardware, you will need to control your Ethernet or USB modules. If you choose this, it will take a lot of time to simply understand the Nios II/Tripple Speed Ethernet MAC/PHY MDIO configuration. If you are not familiar with any of it, this might take you a year or so to finish. I would recommend using Linux or Altera/Micruim's RTOS since you would not have to start from scratch. It would let you focus on your design. How familiar are you with FPGA development? Do you have help? It took me over a year to build a network processor (full hardware; no RTOS or Linux) while taking classes and writing papers. I'm actually still working on it with correcting timing constraints, since high-speed network packets are sensitive to timing. The Using Triple Speed Ethernet (Altera University Program) and UDP Offload Example (AlteraWiki) are the best places I would start for network processing. Not sure about signal processing.