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idata
Community Manager
1,145 Views

Help with 82574 programming

I have an embedded device on which we use the 82574L. The old version used an Atom 3xxx processor with a PCI bus and the network on an card on the bus. Everything works fine. We have updated to an I7 and PCIe (both are PC104 boards). This is board is not running an OS.

Receiving data works fine. When sending data packets, I am having problems.

Following the data sheet, I setup a transmit ring queue of N descriptors. As I setup each descriptor, I set the tail pointer to beyond the next descriptor.

For the first N tries, it works fine. When the queue rolls over, that buffer never completes.

For N=3, I fill desc[0] and set tail to 1, get status complete in status field readback of head register: 1

fill desc[1] and set tail to 2, get status complete in status field readback of head register: 2

fill desc[2] and set tail to 0, get status complete in status field readback of head register: 3

fill desc[0] and set tail to 1, status never changes, packet is not sent readback of head register: 3

The thing that looks strange is that the I would assume the head register should be wrapping back to 0, but I don't see that.

Note I am NOT writing to the head register (except at initialization time), just reading it.

In the test, there is never more than 1 packet being processed at any one time.

Any hints would be appreciated

Martin

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3 Replies
idata
Community Manager
73 Views

Hello Martindoehring,

 

 

Thank you for posting in Intel Wired Ethernet Communities. This issue involves an embedded device. We recommend that you post in https://embedded.communities.intel.com/community/en Intel Embedded Community to address this issue. We hope this information will be useful to find a solution.

 

 

Best regards,

 

Daniel D

 

Intel Customer Support

 

Agent under contract to Intel
MDoeh
Beginner
73 Views

I have found the problems. It was a misunderstanding of the documentation in the code that I was given. It should never have worked. It was telling the chip that the descriptor queue was 16 times larger than It actually was.

Thanks for the help

idata
Community Manager
73 Views

Hello Martindoehring,

 

 

Thank you for the reply. Glad to see you were able to solve the issue. Please let us know if you have any other concerns.

 

 

Best regards,

 

Daniel D

 

Intel Customer Support

 

Agent under contract to Intel

 

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