How to enable JTAG port on i210?

[MMerl1]

Hi,

We are struggling to get the JTAG chain working on WGI210.

Do we need to set some pins at a particular level before we can activate this? Is there a defined startup sequence needed for this?

Thanks in advance,

Mattias

[idata]

Hi Matme,

I will need to check on this and will update the post if there is any information.rgds,wb

[MMerl1]

Thanks wb! Hope to hear soon from you again :-)

[idata]

HI Matme,

Good day. Further checking, this is usually done with a JTAG USB adapter. if your design does not already have a header included, you can blue wire a header onto the JTAG lines.Thanks,wb

[MMerl1]

Hi wb,

The problem is not the hardware connection. We have that in place in our design.

Our real problem is that the JTAG functionality does not seem to work properly. For example when trying to read out the IDCODE, the TDO stays low.

It seems that the chip stays in BYPASS mode.

We are not sure if we need to pull additional lines beside the JTAG lines to a level in order to get this working.

Best regards,

Mattias

[idata]

Hi Mattias,

Thank you for the clarification. I will check on this then update you.rgds,wb

[idata]

Hi Mattias,

Just want to double check if you have look further into the data sheet for sections relatesto JTAG, do you have a reference schematic? rgds,wb

[MMerl1]

Hi,

Yes, we have all the documentation that is available (datasheet/reference schematics/ production images...).

In the mean time we found out by experimenting that we need to assert the LAN_PWR_GOOD signal in order to get a proper response. This is not mentioned in the datasheet.

Also in the reference schematics, there is some info at the NVM_SK pin that we cannot relate to the documentation but seems to be linked to the JTAG interface:

NVM_SK=JTAG MODE

JTAG_MAIN->PU(INT)

JTAG_RSVD->PD (R20)

What does this mean? Where are the details described?

Clearly, we are missing a piece of information regarding this topic.

Best regards,

Mattias

[idata]

Hi Mattias,

Thank you for the clarification. Will further check on this.rgds,wb

[idata]

Hi Mattias,

Good day. The LAN_PWR_GOOD is defined as holding the entire chip in reset, so this needs to be asserted for the chip to come up. Just to double check are you trying to bring up BSDL? Is there a Pullup on JTDO?Thanks,wb

[MMerl1]

Hi,

We need to hold the chip in reset (LAN_PWR_GOOD = low) before we can get the BSDL to work properly... this is NOT stated in the documentation. Is this the right way to activate? Where is it described?

Pullup on TDO is in place.

Please also clarify what:

NVM_SK=JTAG MODE

JTAG_MAIN->PU(INT)

JTAG_RSVD->PD (R20)

means in the reference schematics.

Mattias

[idata]

Hi Mattias,

Thank you for the clarification. I will check on this and update the thread, as additional information

For th JTAG mode. There is an internal Pull Up (PU(int) for normal JTAG mode.

If you add in R20, it changes the mode to the RSVD mode. RSVD mode provides for more in depth testing.

BSDL testing would be the normal JTAG mode.

rgds,

wb

[JOu4]

Hi, today we also can't get the JTAG chain to work. do you have any progress?

[idata]

Hi Mattias,

I am sorry this is still under investigation, no further update yet. Apologize for the inconvenience.rgds,wb

[MMerl1]

Hi wb,

How much time do you think this will take?

[idata]

Hi Mattias,

Apologize for the delay. We are still investigating on this, no timeline yet. Rest assured we are looking into this.rgdswb

[idata]

HI Mattias,

Good day. Further checking, I apologize that we don't have details or documentation about BDSL you are looking for, you may need to find other alternative on how to utilize it, apologize for any the inconvenience this might have caused.rgds,wb

[idata]

Hi Mattias,

Good day. Please let me know if further assistance are needed.rgds,wb

[MMerl1 · Accepted solution]

Hi,

So what you are saying is that there is no documentation on how to use the JTAG? Users (like us) have to experiment and pull some random signals without knowing what should be done.

We have a setup now where we keep the component in reset (lan_pwr_good low) and then the BSDL seems to react.

I find it disturbing that after 2 months, the only useful response we got is that there is no documentation... Next time I'll think twice before using Intel components

Best regards,

Mattias

[NDeLa2]

Hi @MMerl1 I just want to state my thanks for you posting your experience with the i210 here. I recently had trouble bringing up JTAG on the i210 and did not have any success until stumbling upon your forum post. I also use Intel 82580 on my design, which gives LAN_PWR_GOOD as a compliance pin and the BSDL states it should be pulled high (like ref design for i210 shows) - so I would never have thought to drive LAN_PWR_GOOD low on the i210 to get JTAG working. Thanks again.

Intel should really think about updating the JTAG info for this chip...

[MMerl1]

Haha, I forgot all about this one.

Glad to see that you also got it working, @NDeLa2 .

But also sad to see that after 5 years, there still is no update on the documentation...

In the end, I kept my word. Haven't used new intel components ever since