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Hi,
We have an Intel E810-C 4x25Gbps QSFP 100G Ethernet NIC that we're using to transfer uni-directional data between a link partner (FPGA) and a server, hosting the NIC. Our target rate is ~40Gbps
We're currently seeing a small but increasing number of dropped RX packets on the adapter when we query the nic statistics through ethtool.
To help isolate if the problem is hardware or software related, we'd like to place the Intel NIC into transceiver loopback, to enable use of a traffic bist on the master (FPGA). I.e. loop the RX data back to TX within the E810.
It sounds like this is possible, but nothing is showing up in manpages for the adapter to suggest how to enable it.
Here's some version info for our NIC:
0000:99:00.1 Ethernet controller: Intel Corporation Ethernet Controller E810-C for QSFP (rev 02)
driver: ice
version: 1.15.4
firmware-version: 4.30 0x8001bcf8 1.3429.0
expansion-rom-version:
bus-info: 0000:99:00.0
supports-statistics: yes
supports-test: yes
supports-eeprom-access: yes
supports-register-dump: yes
supports-priv-flags: yes
Thanks in advance,
Adrian
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Hello Team,
Greetings from Intel!
Thank you for your response. Regarding your query, I wanted to inform you that we are using an Intel E810-C 4x25Gbps QSFP 100G Ethernet NIC to transfer uni-directional data between a link partner (FPGA) and a server hosting the NIC, I would suggest posting your query on the FPGA Forum for further assistance.
Kindly refer to the below link to post your query.
Intel Community - FPGAs and Programmable Solutions
Regards,
Amina
Intel Customer Support Technician

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